mirror of
https://github.com/google0101-ryan/Emotional.git
synced 2024-06-23 14:43:20 -04:00
Added first instruction
This commit is contained in:
Your Name
parent
1bbe22910c
commit
cb5ecc4b2a
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@ -19,7 +19,9 @@ set(SOURCES src/main.cpp
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src/app/Application.cpp
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src/emu/memory/Bus.cpp
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src/emu/System.cpp
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src/emu/cpu/ee/EmotionEngine.cpp)
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src/emu/cpu/ee/EmotionEngine.cpp
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src/emu/cpu/ee/x64/reg_alloc.cpp
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src/emu/cpu/ee/x64/emit.cpp)
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set(CMAKE_BUILD_TYPE Debug)
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2951
src/3rdparty/xbyak/xbyak.h
vendored
Normal file
2951
src/3rdparty/xbyak/xbyak.h
vendored
Normal file
File diff suppressed because it is too large
Load diff
258
src/3rdparty/xbyak/xbyak_bin2hex.h
vendored
Normal file
258
src/3rdparty/xbyak/xbyak_bin2hex.h
vendored
Normal file
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@ -0,0 +1,258 @@
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enum {
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B00000000= 0,
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B00000001= 1,
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B00000010= 2,
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B00000011= 3,
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B00000100= 4,
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B00000101= 5,
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B00000110= 6,
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B00000111= 7,
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B00001000= 8,
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B00001001= 9,
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B00001010= 10,
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B00001011= 11,
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B00001100= 12,
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B00001101= 13,
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B00001110= 14,
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B00001111= 15,
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B00010000= 16,
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B00010001= 17,
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B00010010= 18,
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B00010011= 19,
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B00010100= 20,
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B00010101= 21,
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B00010110= 22,
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B00010111= 23,
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B00011000= 24,
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B00011001= 25,
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B00011010= 26,
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B00011011= 27,
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B00011100= 28,
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B00011101= 29,
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B00011110= 30,
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B00011111= 31,
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B00100000= 32,
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B00100001= 33,
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B00100010= 34,
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B00100011= 35,
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B00100100= 36,
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B00100101= 37,
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B00100110= 38,
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B00100111= 39,
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B00101000= 40,
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B00101001= 41,
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B00101010= 42,
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B00101011= 43,
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B00101100= 44,
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B00101101= 45,
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B00101110= 46,
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B00101111= 47,
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B00110000= 48,
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B00110001= 49,
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B00110010= 50,
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B00110011= 51,
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B00110100= 52,
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B00110101= 53,
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B00110110= 54,
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B00110111= 55,
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B00111000= 56,
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B00111001= 57,
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B00111010= 58,
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B00111011= 59,
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B00111100= 60,
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B00111101= 61,
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B00111110= 62,
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B00111111= 63,
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B01000000= 64,
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B01000001= 65,
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B01000010= 66,
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B01000011= 67,
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B01000100= 68,
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B01000101= 69,
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B01000110= 70,
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B01000111= 71,
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B01001000= 72,
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B01001001= 73,
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B01001010= 74,
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B01001011= 75,
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B01001100= 76,
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B01001101= 77,
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B01001110= 78,
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B01001111= 79,
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B01010000= 80,
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B01010001= 81,
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B01010010= 82,
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B01010011= 83,
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B01010100= 84,
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B01010101= 85,
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B01010110= 86,
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B01010111= 87,
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B01011000= 88,
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B01011001= 89,
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B01011010= 90,
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B01011011= 91,
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B01011100= 92,
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B01011101= 93,
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B01011110= 94,
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B01011111= 95,
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B01100000= 96,
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B01100001= 97,
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B01100010= 98,
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B01100011= 99,
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B01100100= 100,
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B01100101= 101,
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B01100110= 102,
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B01100111= 103,
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B01101000= 104,
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B01101001= 105,
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B01101010= 106,
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B01101011= 107,
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B01101100= 108,
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B01101101= 109,
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B01101110= 110,
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B01101111= 111,
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B01110000= 112,
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B01110001= 113,
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B01110010= 114,
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B01110011= 115,
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B01110100= 116,
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B01110101= 117,
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B01110110= 118,
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B01110111= 119,
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B01111000= 120,
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B01111001= 121,
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B01111010= 122,
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B01111011= 123,
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B01111100= 124,
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B01111101= 125,
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B01111110= 126,
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B01111111= 127,
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B10000000= 128,
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B10000001= 129,
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B10000010= 130,
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B10000011= 131,
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B10000100= 132,
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B10000101= 133,
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B10000110= 134,
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B10000111= 135,
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B10001000= 136,
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B10001001= 137,
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B10001010= 138,
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B10001011= 139,
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B10001100= 140,
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B10001101= 141,
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B10001110= 142,
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B10001111= 143,
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B10010000= 144,
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B10010001= 145,
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B10010010= 146,
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B10010011= 147,
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B10010100= 148,
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B10010101= 149,
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B10010110= 150,
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B10010111= 151,
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B10011000= 152,
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B10011001= 153,
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B10011010= 154,
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B10011011= 155,
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B10011100= 156,
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B10011101= 157,
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B10011110= 158,
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B10011111= 159,
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B10100000= 160,
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B10100001= 161,
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B10100010= 162,
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B10100011= 163,
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B10100100= 164,
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B10100101= 165,
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B10100110= 166,
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B10100111= 167,
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B10101000= 168,
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B10101001= 169,
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B10101010= 170,
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B10101011= 171,
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B10101100= 172,
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B10101101= 173,
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B10101110= 174,
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B10101111= 175,
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B10110000= 176,
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B10110001= 177,
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B10110010= 178,
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B10110011= 179,
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B10110100= 180,
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B10110101= 181,
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B10110110= 182,
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B10110111= 183,
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B10111000= 184,
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B10111001= 185,
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B10111010= 186,
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B10111011= 187,
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B10111100= 188,
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B10111101= 189,
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B10111110= 190,
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B10111111= 191,
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B11000000= 192,
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B11000001= 193,
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B11000010= 194,
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B11000011= 195,
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B11000100= 196,
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B11000101= 197,
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B11000110= 198,
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B11000111= 199,
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B11001000= 200,
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B11001001= 201,
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B11001010= 202,
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B11001011= 203,
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B11001100= 204,
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B11001101= 205,
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B11001110= 206,
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B11001111= 207,
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B11010000= 208,
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B11010001= 209,
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B11010010= 210,
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B11010011= 211,
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B11010100= 212,
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B11010101= 213,
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B11010110= 214,
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B11010111= 215,
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B11011000= 216,
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B11011001= 217,
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B11011010= 218,
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B11011011= 219,
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B11011100= 220,
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B11011101= 221,
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B11011110= 222,
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B11011111= 223,
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B11100000= 224,
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B11100001= 225,
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B11100010= 226,
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B11100011= 227,
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B11100100= 228,
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B11100101= 229,
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B11100110= 230,
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B11100111= 231,
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B11101000= 232,
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B11101001= 233,
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B11101010= 234,
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B11101011= 235,
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B11101100= 236,
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B11101101= 237,
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B11101110= 238,
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B11101111= 239,
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B11110000= 240,
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B11110001= 241,
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B11110010= 242,
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B11110011= 243,
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B11110100= 244,
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B11110101= 245,
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B11110110= 246,
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B11110111= 247,
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B11111000= 248,
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B11111001= 249,
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B11111010= 250,
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B11111011= 251,
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B11111100= 252,
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B11111101= 253,
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B11111110= 254,
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B11111111= 255
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};
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2331
src/3rdparty/xbyak/xbyak_mnemonic.h
vendored
Normal file
2331
src/3rdparty/xbyak/xbyak_mnemonic.h
vendored
Normal file
File diff suppressed because it is too large
Load diff
1000
src/3rdparty/xbyak/xbyak_util.h
vendored
Normal file
1000
src/3rdparty/xbyak/xbyak_util.h
vendored
Normal file
File diff suppressed because it is too large
Load diff
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@ -48,4 +48,6 @@ void Application::Exit(int code)
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}
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void Application::Exit()
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{}
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{
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System::Dump();
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}
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@ -35,4 +35,9 @@ void System::Run()
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{
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while (1)
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EmotionEngine::Clock();
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}
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}
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void System::Dump()
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{
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EmotionEngine::Dump();
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}
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@ -11,5 +11,6 @@ void LoadBios(std::string biosName);
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void Reset();
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void Run();
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void Dump();
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}
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@ -1,55 +1,34 @@
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#include "EmotionEngine.h"
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#include <emu/memory/Bus.h>
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#include <emu/cpu/ee/x64/emit.h>
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namespace EE_JIT
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{
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enum IRInstrs
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void JIT::EmitBNE(uint32_t instr, EE_JIT::IRInstruction &i)
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{
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MOV = 0,
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NOP = 0,
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SLTI = 0,
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};
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printf("bne\n");
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struct IRValue
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{
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public:
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enum Type
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{
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Imm,
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Reg,
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Cop0Reg,
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FP
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};
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private:
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union
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{
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uint32_t imm;
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int register_num;
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float fp_value;
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int cop_regnum;
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} value;
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int rt = (instr >> 16) & 0x1F;
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int rs = (instr >> 21) & 0x1F;
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Type type;
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public:
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IRValue(Type type)
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: type(type) {}
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IRValue dest = IRValue(IRValue::Reg);
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IRValue source = IRValue(IRValue::Reg);
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IRValue imm = IRValue(IRValue::Imm);
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bool IsImm() {return type == Imm;}
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// Can be used for guest and COP0 registers
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void SetReg(uint32_t reg) {value.register_num = reg;}
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void SetImm(uint16_t imm) {value.imm = (int32_t)(int16_t)imm;}
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};
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source.SetReg(rs);
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dest.SetReg(rt);
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imm.SetImm(instr & 0xffff);
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struct IRInstruction
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{
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uint8_t instr;
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// Arguments are right -> left
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std::vector<IRValue> args;
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};
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i = IRInstruction::Build({dest, source, imm}, IRInstrs::BranchConditional);
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i.b_type = IRInstruction::BranchType::NE;
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cur_block->ir.push_back(i);
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}
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void JIT::EmitSLTI(uint32_t instr, EE_JIT::IRInstruction &i)
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{
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printf("slti\n");
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int rt = (instr >> 16) & 0x1F;
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int rs = (instr >> 21) & 0x1F;
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@ -60,10 +39,7 @@ void JIT::EmitSLTI(uint32_t instr, EE_JIT::IRInstruction &i)
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dest.SetReg(rt);
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imm.SetImm(instr & 0xffff);
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i.instr = IRInstrs::SLTI;
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i.args.push_back(imm);
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i.args.push_back(source);
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i.args.push_back(dest);
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i = IRInstruction::Build({dest, source, imm}, IRInstrs::SLTI);
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cur_block->ir.push_back(i);
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}
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@ -87,6 +63,8 @@ void JIT::EmitCOP0(uint32_t instr, EE_JIT::IRInstruction &i)
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void JIT::EmitMFC0(uint32_t instr, EE_JIT::IRInstruction& i)
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{
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printf("mfc0\n");
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int rd = (instr >> 11) & 0x1F;
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int rt = (instr >> 16) & 0x1F;
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@ -95,25 +73,19 @@ void JIT::EmitMFC0(uint32_t instr, EE_JIT::IRInstruction& i)
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dest.SetReg(rd);
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src.SetReg(rt);
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i.instr = IRInstrs::MOV;
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i.args.push_back(src);
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i.args.push_back(dest);
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i = IRInstruction::Build({dest, src}, IRInstrs::MOV);
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cur_block->ir.push_back(i);
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}
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void JIT::EmitIR(uint32_t instr)
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{
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if (!cur_block)
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{
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cur_block = new Block;
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}
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EE_JIT::IRInstruction current_instruction;
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if (instr == 0)
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{
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printf("nop\n");
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current_instruction.instr = NOP;
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cur_block->ir.push_back(current_instruction);
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return;
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@ -123,6 +95,9 @@ void JIT::EmitIR(uint32_t instr)
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switch (opcode)
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{
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case 0x05:
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EmitBNE(instr, current_instruction);
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break;
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case 0x0A:
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EmitSLTI(instr, current_instruction);
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break;
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@ -135,6 +110,26 @@ void JIT::EmitIR(uint32_t instr)
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}
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}
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void JIT::EmitPrequel()
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{
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if (!cur_block)
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{
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cur_block = new Block;
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}
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auto i = IRInstruction::Build({}, IRInstrs::SaveHostRegs);
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cur_block->ir.push_back(i);
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}
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void JIT::EmitDone()
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{
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auto i = IRInstruction::Build({}, IRInstrs::RestoreHostRegs);
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cur_block->ir.push_back(i);
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blockCache.push_back(cur_block);
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EE_JIT::emit->TranslateBlock(cur_block);
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}
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}
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EE_JIT::JIT jit;
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@ -149,15 +144,53 @@ void Reset()
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state.pc = 0xBFC00000;
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state.next_pc = 0xBFC00004;
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EE_JIT::emit = new EE_JIT::Emitter();
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}
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bool IsBranch(uint32_t instr)
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{
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uint8_t opcode = (instr >> 26) & 0x3F;
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switch (opcode)
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{
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case 0x05:
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return true;
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default:
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return false;
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}
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}
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void Clock()
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{
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uint32_t instr = Bus::Read32(state.pc);
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state.pc = state.next_pc;
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state.next_pc += 4;
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jit.EmitPrequel();
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jit.EmitIR(instr);
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bool isBranch = false;
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bool isBranchDelayed = false;
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do
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{
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uint32_t instr = Bus::Read32(state.pc);
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state.pc = state.next_pc;
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state.next_pc += 4;
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jit.EmitIR(instr);
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isBranch = isBranchDelayed;
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isBranchDelayed = IsBranch(instr);
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} while (!isBranch);
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|
||||
jit.EmitDone();
|
||||
exit(1);
|
||||
}
|
||||
|
||||
void Dump()
|
||||
{
|
||||
EE_JIT::emit->Dump();
|
||||
}
|
||||
|
||||
ProcessorState* GetState()
|
||||
{
|
||||
return &state;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,26 +7,95 @@
|
|||
namespace EE_JIT
|
||||
{
|
||||
|
||||
struct IRInstruction;
|
||||
enum IRInstrs
|
||||
{
|
||||
MOV = 0,
|
||||
NOP = 1,
|
||||
SLTI = 2,
|
||||
SaveHostRegs = 3,
|
||||
RestoreHostRegs = 4,
|
||||
BranchConditional = 5,
|
||||
};
|
||||
|
||||
struct IRValue
|
||||
{
|
||||
public:
|
||||
enum Type
|
||||
{
|
||||
Imm,
|
||||
Reg,
|
||||
Cop0Reg,
|
||||
FP
|
||||
};
|
||||
private:
|
||||
union
|
||||
{
|
||||
uint32_t imm;
|
||||
int register_num;
|
||||
float fp_value;
|
||||
int cop_regnum;
|
||||
} value;
|
||||
|
||||
Type type;
|
||||
public:
|
||||
IRValue(Type type)
|
||||
: type(type) {}
|
||||
|
||||
bool IsImm() {return type == Imm;}
|
||||
bool IsCop0() {return type == Cop0Reg;}
|
||||
// Can be used for guest and COP0 registers
|
||||
void SetReg(uint32_t reg) {value.register_num = reg;}
|
||||
void SetImm(uint16_t imm) {value.imm = (int32_t)(int16_t)imm;}
|
||||
|
||||
uint32_t GetImm() {return value.imm;}
|
||||
uint32_t GetReg() {return value.register_num;}
|
||||
};
|
||||
|
||||
struct IRInstruction
|
||||
{
|
||||
uint8_t instr;
|
||||
// Arguments are right -> left
|
||||
std::vector<IRValue> args;
|
||||
|
||||
enum BranchType
|
||||
{
|
||||
NE = 0,
|
||||
} b_type;
|
||||
|
||||
static IRInstruction Build(std::vector<IRValue> args, uint8_t i_type)
|
||||
{
|
||||
IRInstruction i;
|
||||
i.instr = i_type;
|
||||
i.args = args;
|
||||
|
||||
return i;
|
||||
}
|
||||
};
|
||||
|
||||
struct Block
|
||||
{
|
||||
uint32_t guest_start;
|
||||
std::vector<IRInstruction> ir;
|
||||
};
|
||||
|
||||
class JIT
|
||||
{
|
||||
private:
|
||||
struct Block
|
||||
{
|
||||
uint32_t guest_start;
|
||||
std::vector<IRInstruction> ir;
|
||||
};
|
||||
|
||||
Block* cur_block;
|
||||
std::vector<Block*> blockCache;
|
||||
|
||||
void EmitSLTI(uint32_t instr, EE_JIT::IRInstruction& i);
|
||||
void EmitCOP0(uint32_t instr, EE_JIT::IRInstruction& i);
|
||||
void EmitBNE(uint32_t instr, EE_JIT::IRInstruction& i); // 0x05
|
||||
void EmitSLTI(uint32_t instr, EE_JIT::IRInstruction& i); // 0x0A
|
||||
void EmitCOP0(uint32_t instr, EE_JIT::IRInstruction& i); // 0x10
|
||||
|
||||
|
||||
void EmitMFC0(uint32_t instr, EE_JIT::IRInstruction& i);
|
||||
public:
|
||||
void EmitIR(uint32_t instr);
|
||||
|
||||
void EmitPrequel();
|
||||
void EmitDone();
|
||||
};
|
||||
|
||||
}
|
||||
|
|
@ -37,10 +106,13 @@ namespace EmotionEngine
|
|||
struct ProcessorState
|
||||
{
|
||||
uint128_t regs[32];
|
||||
uint32_t cop0_regs[32];
|
||||
uint32_t pc, next_pc;
|
||||
};
|
||||
|
||||
void Reset();
|
||||
void Clock();
|
||||
void Dump();
|
||||
ProcessorState* GetState();
|
||||
|
||||
}
|
||||
98
src/emu/cpu/ee/x64/emit.cpp
Normal file
98
src/emu/cpu/ee/x64/emit.cpp
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
#include "emit.h"
|
||||
#include <sys/mman.h>
|
||||
#include <emu/cpu/ee/EmotionEngine.h>
|
||||
#include <fstream>
|
||||
|
||||
EE_JIT::Emitter* EE_JIT::emit;
|
||||
|
||||
void EE_JIT::Emitter::EmitMov(IRInstruction i)
|
||||
{
|
||||
if (i.args[1].IsImm()) // Lui
|
||||
{
|
||||
Xbyak::Reg64 reg_ptr = Xbyak::Reg64(reg_alloc->AllocHostRegister());
|
||||
auto offset = ((offsetof(EmotionEngine::ProcessorState, regs)) + (i.args[1].GetReg() * sizeof(uint128_t) + offsetof(uint128_t, u32)));
|
||||
cg->lea(reg_ptr, cg->ptr[cg->rax + offset]);
|
||||
cg->mov(cg->dword[reg_ptr], i.args[0].GetImm());
|
||||
}
|
||||
else if (i.args[1].IsCop0()) // Mfc0
|
||||
{
|
||||
Xbyak::Reg64 ee_reg_ptr = Xbyak::Reg64(reg_alloc->AllocHostRegister());
|
||||
Xbyak::Reg64 cop_reg_ptr = Xbyak::Reg64(reg_alloc->AllocHostRegister());
|
||||
Xbyak::Reg64 ee_reg_value = Xbyak::Reg64(reg_alloc->AllocHostRegister());
|
||||
auto dest_offset = ((offsetof(EmotionEngine::ProcessorState, regs)) + (i.args[0].GetReg() * sizeof(uint128_t) + offsetof(uint128_t, u32)));
|
||||
auto src_offset = ((offsetof(EmotionEngine::ProcessorState, cop0_regs)) + (i.args[1].GetReg() * sizeof(uint32_t)));
|
||||
cg->lea(cop_reg_ptr, cg->ptr[cg->rax + src_offset]);
|
||||
cg->mov(ee_reg_value, cg->dword[cop_reg_ptr]);
|
||||
cg->lea(ee_reg_ptr, cg->ptr[cg->rax + dest_offset]);
|
||||
cg->mov(cg->dword[ee_reg_ptr], ee_reg_value);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf("[emu/JIT]: Unknown MOV format\n");
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
void EE_JIT::Emitter::EmitSaveHostRegs()
|
||||
{
|
||||
for (int i = 0; i < 8; i++)
|
||||
if (i != 4)
|
||||
cg->push(Xbyak::Reg64(i));
|
||||
|
||||
cg->mov(cg->rbp, reinterpret_cast<uint64_t>(EmotionEngine::GetState()));
|
||||
}
|
||||
|
||||
void EE_JIT::Emitter::EmitIR(IRInstruction i)
|
||||
{
|
||||
reg_alloc->Reset();
|
||||
|
||||
switch (i.instr)
|
||||
{
|
||||
case SaveHostRegs:
|
||||
EmitSaveHostRegs();
|
||||
break;
|
||||
case MOV:
|
||||
EmitMov(i);
|
||||
break;
|
||||
default:
|
||||
printf("[JIT/Emit]: Unknown IR instruction 0x%02x\n", i.instr);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
|
||||
EE_JIT::Emitter::Emitter()
|
||||
{
|
||||
base = (uint8_t*)mmap(nullptr, 0xffffffff, PROT_EXEC | PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
|
||||
|
||||
if (base == MAP_FAILED)
|
||||
{
|
||||
printf("[JIT/Emit]: Failed to map base! %s\n", strerror(errno));
|
||||
exit(1);
|
||||
}
|
||||
|
||||
cg = new Xbyak::CodeGenerator(0xffffff, (void*)base);
|
||||
reg_alloc = new RegisterAllocator();
|
||||
reg_alloc->Reset();
|
||||
}
|
||||
|
||||
void EE_JIT::Emitter::Dump()
|
||||
{
|
||||
std::ofstream dump("out.bin");
|
||||
for (size_t i = 0; i < cg->getSize(); i++)
|
||||
{
|
||||
dump << cg->getCode()[i];
|
||||
}
|
||||
|
||||
dump.flush();
|
||||
dump.close();
|
||||
|
||||
munmap(base, 0xffffffff);
|
||||
}
|
||||
|
||||
void EE_JIT::Emitter::TranslateBlock(Block *block)
|
||||
{
|
||||
for (auto& i : block->ir)
|
||||
{
|
||||
EmitIR(i);
|
||||
}
|
||||
}
|
||||
31
src/emu/cpu/ee/x64/emit.h
Normal file
31
src/emu/cpu/ee/x64/emit.h
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
#include <emu/cpu/ee/x64/reg_alloc.h>
|
||||
#include <3rdparty/xbyak/xbyak.h>
|
||||
|
||||
namespace EE_JIT
|
||||
{
|
||||
|
||||
struct Block;
|
||||
struct IRInstruction;
|
||||
|
||||
class Emitter
|
||||
{
|
||||
private:
|
||||
Xbyak::CodeGenerator* cg;
|
||||
uint8_t* base;
|
||||
RegisterAllocator* reg_alloc;
|
||||
|
||||
void EmitSaveHostRegs();
|
||||
void EmitMov(IRInstruction i);
|
||||
void EmitIR(IRInstruction i);
|
||||
public:
|
||||
Emitter();
|
||||
void Dump();
|
||||
void TranslateBlock(Block* block);
|
||||
};
|
||||
|
||||
extern Emitter* emit;
|
||||
|
||||
}
|
||||
31
src/emu/cpu/ee/x64/reg_alloc.cpp
Normal file
31
src/emu/cpu/ee/x64/reg_alloc.cpp
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
#include "reg_alloc.h"
|
||||
#include <cstdio>
|
||||
#include <cstdlib>
|
||||
|
||||
RegisterAllocator::RegisterAllocator()
|
||||
{
|
||||
Reset();
|
||||
// Here just in case I have to do any initialization in the future
|
||||
}
|
||||
|
||||
void RegisterAllocator::Reset()
|
||||
{
|
||||
used_registers.fill(false);
|
||||
used_registers_8.fill(false);
|
||||
used_registers[RBP] = true;
|
||||
}
|
||||
|
||||
int RegisterAllocator::AllocHostRegister()
|
||||
{
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
if (!used_registers[i])
|
||||
{
|
||||
used_registers[i] = true;
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
printf("[JIT/RegAlloc]: Ran out of host registers!\n");
|
||||
exit(1);
|
||||
}
|
||||
29
src/emu/cpu/ee/x64/reg_alloc.h
Normal file
29
src/emu/cpu/ee/x64/reg_alloc.h
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
#include <array>
|
||||
|
||||
class RegisterAllocator
|
||||
{
|
||||
private:
|
||||
std::array<bool, 8> used_registers;
|
||||
// Due to how 8-bit registers map, we have a seperate array
|
||||
std::array<bool, 8> used_registers_8;
|
||||
|
||||
enum HostRegisters64
|
||||
{
|
||||
RAX,
|
||||
RCX,
|
||||
RDX,
|
||||
RBX,
|
||||
RSP,
|
||||
RBP,
|
||||
RSI,
|
||||
RDI
|
||||
};
|
||||
public:
|
||||
RegisterAllocator();
|
||||
void Reset();
|
||||
|
||||
int AllocHostRegister();
|
||||
};
|
||||
Loading…
Reference in a new issue