refractionpcsx2
1b2d6503c9
EE JIT: Clamp FPU ops
2020-05-16 20:52:25 +01:00
refractionpcsx2
3d993ca42c
Small fix to handling of VIF STOP
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Added die condition on VIF Force Break (Need to find a game that uses it)
Handle situation better where VIF STOP and I-Bit stall can happen at the same time
2020-05-16 01:03:15 +01:00
refractionpcsx2
54ed710a92
remove COP2 cycle counting, now uses VU0 and EE cycles to sync
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VU run functions no longer take cycles as a parameter
COP2 stalls now also stall the EE for the same number of cycles
start VU program now takes a cycle delay to account for DMA timings when using MSCAL
Keep VU's showing as "running" if the VU cycles overran the EE cycle count when ending a Micro Program, Solves some COP2 timing issues
stop PATH2 constantly deactivating itself (mainly cleans up logging)
Fix PATH1 requests from VU
2020-05-15 16:41:29 +01:00
PSI-Rockin
5765ccbdab
EE/SIF: Setup framework for RPC logging
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Take absolute value of syscall ID (some syscalls are negative)
2020-05-13 20:00:00 -04:00
PSISP
febc810934
Merge pull request #364 from refractionpcsx2/vu0_jit_take2
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VU: Implement JIT for VU0
2020-05-09 19:11:40 -04:00
refractionpcsx2
055c19394f
Put instruction count in and MAX_BLOCK_SIZE setting for easy tweaking of block sizes
2020-05-10 00:00:46 +01:00
PSISP
12be59080d
Merge pull request #387 from turtleli/ipu
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IPU: Implement PACK command and dithering
2020-05-09 15:55:39 -04:00
Jonathan Li
1f2abb463d
IPU: Implement PACK command
2020-05-09 01:30:04 +01:00
PSISP
72feb6d100
Merge pull request #390 from Souzooka/jalr
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EE JIT: Use destination field of JALR (implied ra) as link reg
2020-05-05 18:12:24 -04:00
PSISP
c522b0dd47
Merge pull request #389 from Souzooka/bal
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EE JIT: Ensure RA doesn't get trashed for BGTZAL/BLTZAL
2020-05-05 18:11:31 -04:00
dakotachasesmith
99db518522
Use destination field of JALR (implied ra) as link reg
2020-05-05 01:11:35 -10:00
dakotachasesmith
7b9d7fe33d
EE JIT: Ensure RA doesn't get trashed for BGTZAL/BLTZAL
2020-05-05 00:52:20 -10:00
PSISP
34a519438d
Merge pull request #388 from PSI-Rockin/eejit_ra_fix
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EE JIT: Ensure RA doesn't get trashed for JAL(R)
2020-05-05 01:50:54 -04:00
PSI-Rockin
3539e416b9
EE JIT: Ensure RA doesn't get trashed for JAL(R)
2020-05-04 22:39:14 -04:00
Jonathan Li
bf0e09ce09
IPU: Implement dithering
2020-05-04 22:04:46 +01:00
Jonathan Li
6f3ee32c35
IPU: Move RGB32 to RGB16 conversion to a separate function
2020-05-04 22:04:28 +01:00
Jonathan Li
1f0bcab857
IPU: Add RGB_BLOCK_SIZE constant
2020-05-04 22:04:13 +01:00
Jonathan Li
778aa0841a
IPU: Change BLOCK_SIZE to constexpr RAW_BLOCK_SIZE
2020-05-04 22:03:59 +01:00
PSISP
e4b4313be8
Merge pull request #386 from refractionpcsx2/eejit_integer_minmax
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EE JIT: Use integer instructions for FPU MIN/MAX. Prevents "denormals" from being flushed
2020-05-04 00:09:20 -04:00
PSISP
86f3fa218d
Merge pull request #385 from tadanokojin/gsthread-reset
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GS: properly reset the gsthread
2020-05-04 00:08:33 -04:00
refractionpcsx2
8d79125256
Avoid Dest = Source
2020-05-04 00:09:18 +01:00
refractionpcsx2
36350c3476
Small simplification, no need to use BLEND
2020-05-03 23:32:29 +01:00
refractionpcsx2
63acd0e6e2
Convert EE JIT FPU Min/Max to Integer
2020-05-03 23:27:37 +01:00
Kojin
534ea525d1
gs: properly reset the gsthread
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Previous code only called reset on gsthread at the top of the event loop.
This commit allows reset to be called from the core thread.
Additionally fixes interlace artifacts when booting a game after having had previously run something.
2020-05-03 04:36:55 -04:00
PSISP
099af62e89
Merge pull request #378 from tadanokojin/gs-priv
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GS: Partially Implement and Log Undocumented Privileged Registers
2020-05-02 21:16:23 -04:00
PSISP
2303dbfa49
Merge pull request #365 from refractionpcsx2/better_path3_masking
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GIF: PATH3 masking more in line with the manual now
GIF/VIF: Implement reset (fixes Dynasty Warriors 5 hang)
2020-05-02 20:44:09 -04:00
PSISP
3670ff4eb9
Merge pull request #382 from tadanokojin/qt-gamelist-ordering
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Qt: Fix gamelist order
2020-05-02 00:26:39 -04:00
PSISP
77a9a6cc74
Merge pull request #363 from refractionpcsx2/eejit_double_interlock
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EE JIT: Fix double interlock checks on CTC2/QMTC2
Fixes My Street and Soul Calibur 2
2020-05-02 00:21:10 -04:00
refractionpcsx2
fe757715ce
removed old comment
2020-05-01 22:19:12 +01:00
refractionpcsx2
2632250eb4
EE JIT: Disable Branch Pipeline bug. ( #383 )
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Testing on the PS2 reveals this doesn't actually happen in several thousands of branches tested
2020-05-01 15:27:51 -04:00
Kojin
13ab843239
qt: fix gamelist order
2020-04-30 19:55:35 -04:00
PSISP
4f7206c0e8
Merge pull request #381 from refractionpcsx2/clut_fix_finale
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GS: Remove the clut load of context change rubbish
2020-04-30 19:06:34 -04:00
refractionpcsx2
2732a1658e
Remove the clut load of context change rubbish
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Make sure CLUT only uploads to the maximum number of entries the cache can hold, don't loop around
2020-04-30 23:58:06 +01:00
PSISP
5e6cb4a984
Merge pull request #379 from Souzooka/ldr
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EE JIT: Properly destroy top bit on aligned lwl/lwr/ldl/ldr
2020-04-29 19:09:09 -04:00
dakotachasesmith
d20aa3e8bf
Properly destroy top bit on aligned lwl/lwr/ldl/ldr
2020-04-29 11:45:22 -10:00
PSISP
bc6d001cf3
Merge pull request #376 from refractionpcsx2/firewire
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IOP: Add FireWire stub support to help games boot which look for iLink
2020-04-29 14:13:54 -04:00
refractionpcsx2
db92afe858
Clean up firewire.hpp spacing
2020-04-29 08:40:22 +01:00
PSISP
373f12443e
Merge pull request #374 from refractionpcsx2/clut_fixup
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GS: Fix CLUT Reloading with offset
2020-04-28 19:30:52 -04:00
Kojin
404faf04da
gs: die on unrecognized priv write
2020-04-28 16:30:23 -04:00
Kojin
37eeaff4cb
gs: log feedback write registers, die on activation
2020-04-28 16:30:23 -04:00
Kojin
4353af1250
gs: log SRFSH
2020-04-28 16:30:23 -04:00
Kojin
17044061a8
gs: partially implement and log SYNCV
2020-04-28 16:30:18 -04:00
Kojin
9d27c7b009
gs: log SYNCH2
2020-04-28 16:30:16 -04:00
Kojin
64e529c126
gs: partially implement and log SYNCH1
2020-04-28 16:30:16 -04:00
Kojin
cb460225e1
gs: partially implement and log SMODE1
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Also properly reset some registers
2020-04-28 16:30:07 -04:00
Kojin
9da336bef6
gs: implement priv register r/w mirroring
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0x0400-0x07f0 -> 0x0000-0x03f0
0x0800-0x0ff0 -> 0x0000-0x07f0
0x1400-0x17f0 -> 0x1000-0x13f0
0x1800-0x1ff0 -> 0x1000-0x17f0
0x2000-0xfff0 additionally appears mirrored but this range is listed as just "reserved" with no mention of the mirror.
Reads above 0xfff0 are possible but result in a crash on real hw.
tested on gs rev 21
Any read access to an address which isn't mapped to a register marked for reads will read GS CSR.
2020-04-28 04:14:24 -04:00
refractionpcsx2
529405bb7e
Removed some redundant code
2020-04-22 00:04:41 +01:00
refractionpcsx2
b256b747ac
Fix QMake
2020-04-21 22:35:53 +01:00
refractionpcsx2
176b294ebc
Fix up CMake, hopefully
2020-04-21 22:31:34 +01:00
refractionpcsx2
2d9b762535
Comment fix
2020-04-21 22:22:35 +01:00
