mirror of
https://github.com/liuk7071/ChonkyStation.git
synced 2025-04-02 10:52:38 -04:00
891 lines
No EOL
22 KiB
C++
891 lines
No EOL
22 KiB
C++
/* TODO: Software fastmem
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https://wheremyfoodat.github.io/software-fastmem/ */
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#include "memory.h"
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#include <iostream>
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#define log
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#undef log
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#define ENABLE_RAM_MIRRORS
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#undef ENABLE_RAM_MIRRORS
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#pragma warning(disable : 4996)
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void ScheduleVBLANK_(void* dataptr) {
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memory* memoryptr = (memory*)dataptr;
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printf("fuck\n");
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memoryptr->I_STAT |= 1;
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}
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void TMR1IRQ(void* dataptr) {
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memory* memoryptr = (memory*)dataptr;
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memoryptr->I_STAT |= 0b100000;
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memoryptr->CDROM.Scheduler.push(&TMR1IRQ, memoryptr->CDROM.Scheduler.time + 5000, memoryptr);
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////printf("[TIMER]] Sending TMR1 IRQ (stub)\n");
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}
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void TMR2IRQ(void* dataptr) {
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memory* memoryptr = (memory*)dataptr;
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memoryptr->I_STAT |= 0b1000000;
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}
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void DMAIRQ(void* dataptr) {
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memory* memoryptr = (memory*)dataptr;
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memoryptr->I_STAT |= 0b1000;
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memoryptr->DICR |= (1 << 28);
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}
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memory::memory() {
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debug = false;
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}
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memory::~memory() {
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}
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void memory::debug_log(const char* fmt, ...) {
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#ifdef log
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std::va_list args;
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va_start(args, fmt);
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std::vprintf(fmt, args);
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va_end(args);
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#endif
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}
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void memory::debug_warn(const char* fmt, ...) {
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if (debug) {
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SetConsoleTextAttribute(hConsole, FOREGROUND_RED | FOREGROUND_GREEN);
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std::va_list args;
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va_start(args, fmt);
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std::vprintf(fmt, args);
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va_end(args);
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SetConsoleTextAttribute(hConsole, FOREGROUND_RED | FOREGROUND_GREEN | FOREGROUND_BLUE);
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}
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}
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void memory::debug_err(const char* fmt, ...) {
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SetConsoleTextAttribute(hConsole, FOREGROUND_RED);
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std::va_list args;
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va_start(args, fmt);
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std::vprintf(fmt, args);
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va_end(args);
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SetConsoleTextAttribute(hConsole, FOREGROUND_RED | FOREGROUND_GREEN | FOREGROUND_BLUE);
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}
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uint32_t memory::mask_address(const uint32_t addr)
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{
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static const uint32_t ADDR_MASK[] =
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{
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0x7FFFFFFF, // totally my code
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0x1FFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF
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};
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const auto idx = (addr >> 29u);
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return addr & ADDR_MASK[idx];
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}
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uint8_t memory::read(uint32_t addr) {
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uint32_t bytes;
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uint32_t masked_addr = mask_address(addr);
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if (masked_addr == 0xf1000001) {
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return 0;
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}
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if (masked_addr == 0xf1000002) {
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return 0;
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}
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if (masked_addr == 0xf1000003) {
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return 0;
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}
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if (masked_addr >= 0xf1000004 && masked_addr <= 0xf10000ff) {
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return 0;
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}
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if (masked_addr == 0x1F801070) { // I_STAT
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debug_log("[IRQ] Status 8bit read\n");
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return I_STAT;
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}
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// controller
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if (masked_addr == 0x1f801040) { // JOY_RX_DATA
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uint8_t data = pads.ReadRXFIFO();
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debug_warn("[PAD] Read JOY_RX_DATA (0x%x)\n", data);
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return data;
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}
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if (masked_addr == 0x1f801054) { // SIO_STAT
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printf("[SIO] Read SIO_STAT (ignored)\n");
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return 0;
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}
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if (masked_addr == 0x1f801800) { // cdrom status
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//printf("[CDROM] Status register read\n");
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return rand() % 0xff;
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return CDROM.status | (CDROM.cd.drqsts << 6);
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}
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if (masked_addr == 0x1f801801) {
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switch (CDROM.status & 0b11) {
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case 0:
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case 1:
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debug_log("[CDROM] Read response fifo\n");
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return CDROM.read_fifo();
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default:
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printf("Unhandled CDROM read 0x%x index %d", addr, CDROM.status & 0b11);
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exit(0);
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}
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}
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if (masked_addr == 0x1f801803) {
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switch (CDROM.status & 0b11) {
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case 0:
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debug_log("[CDROM] Read IE\n");
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return CDROM.interrupt_enable;
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case 1:
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debug_log("[CDROM] Read IF\n");
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return CDROM.interrupt_flag;
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default:
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printf("Unhandled CDROM read 0x%x index %d", addr, CDROM.status & 0b11);
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exit(0);
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}
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}
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if (masked_addr >= 0x1FC00000 && masked_addr <= 0x1FC00000 + 524288) {
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memcpy(&bytes, &bios[masked_addr & 0x7ffff], sizeof(uint8_t));
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return bytes;
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}
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if (masked_addr >= 0x1f800000 && masked_addr < 0x1f800000 + 1024) {
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memcpy(&bytes, &scratchpad[masked_addr & 0x3ff], sizeof(uint8_t));
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return bytes;
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}
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if (masked_addr >= 0x00000000 && masked_addr < 0x00000000 + 0x200000) {
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memcpy(&bytes, &ram[masked_addr & 0x1fffff], sizeof(uint8_t));
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return bytes;
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}
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#ifdef ENABLE_RAM_MIRRORS
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if (masked_addr >= 0x00200000 && masked_addr < 0x00200000 + 0x200000) {
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memcpy(&bytes, &ram[masked_addr & 0x1fffff], sizeof(uint8_t));
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return bytes;
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}
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#endif
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if (masked_addr >= 0x1F000000 && masked_addr < 0x1F000000 + 0x400) { // return default exp1 value
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return 0xff;
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}
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printf("\nUnhandled read 0x%.8x @ 0x%08x", masked_addr, pc);
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exit(0);
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}
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uint16_t memory::read16(uint32_t addr) {
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uint32_t bytes;
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uint32_t masked_addr = mask_address(addr);
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// SPU stuff
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if (masked_addr == 0x1f801d08) return 0;
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if (masked_addr == 0x1f801d0a) return 0;
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if (masked_addr == 0x1f801d18) return 0;
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if (masked_addr == 0x1f801d1a) return 0;
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//if (patch_b0_15h && (masked_addr == mask_address(button_dest))) printf("test\n");
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// Timer 0 current value
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if (masked_addr == 0x1f801100) {
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//printf("[TIMER] Read timer 0 current value\n");
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tmr1_stub += rand() % 4;
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return tmr1_stub;
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}
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// Timer 1 current value
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if (masked_addr == 0x1f801110) {
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//printf("[TIMER] Read timer 1 current value (stubbed)\n");
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tmr1_stub += rand() % 4;
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return tmr1_stub;
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}
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// Timer 1 counter mode
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if (masked_addr == 0x1f801114) {
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//printf("[TIMER] Read timer 1 counter mode (stubbed)\n");
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return 0;
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}
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if (masked_addr == 0x1f801120) { // timer 2 stuff
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//printf("[TIMER] Read timer 2 current value (stubbed)\n");
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tmr1_stub += rand() % 4;
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return tmr1_stub;
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}
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if (masked_addr == 0x1f801124) {
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//printf("[TIMER] Read timer 2 counter mode (stubbed)\n");
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return 0;
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}
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if (masked_addr == 0x1f801128) {
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//printf("[TIMER] Read timer 2 counter target (stubbed)\n");
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return 0;
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}
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// What is this?
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if (masked_addr == 0x1f801130) return 0;
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// controllers
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if (masked_addr == 0x1f801044) { // JOY_STAT
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uint16_t data = pads.joy_stat;
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debug_warn("[PAD] Read 0x%x from JOY_STAT @ 0x%08x\n", data, pc);
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//return rand() & 0b111;
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return data;
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}
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if (masked_addr == 0x1f80104a) { // JOY_CTRL
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debug_warn("[PAD] Read JOY_CTRL\n");
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return pads.joy_ctrl;
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}
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//if (masked_addr == 0x1f801040) { // JOY_RX_DATA
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// debug_warn("[PAD] Read JOY_RX_DATA\n");
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// return pads.joy_rx_data;
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//}
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if (masked_addr >= 0x1F801D80 && masked_addr <= 0x1F801DBC) { // SPUSTAT
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//printf("[SPU] SPUSTAT read (stubbed)\n");
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return rand() % 0xff;
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}
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if (masked_addr == 0x1F801070) { // I_STAT
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debug_log("[IRQ] Status 16bit read\n");
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return I_STAT;
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}
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if (masked_addr == 0x1f801074) { // I_MASK
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debug_log("[IRQ] Status 16bit read\n");
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return I_MASK;
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}
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if (masked_addr >= 0x1F801C00 && masked_addr <= 0x1F801CfE || masked_addr == 0x1f801d0c && masked_addr <= 0x1f801dfc || masked_addr >= 0x1f801d1c && masked_addr <= 0x1f801dfc) { // more spu registers
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//printf("[SPU] Registers read (stubbed)\n");
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return rand() % 0xff;
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}
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if (masked_addr >= 0x1FC00000 && masked_addr <= 0x1FC00000 + 524288) {
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memcpy(&bytes, &bios[masked_addr & 0x7ffff], sizeof(uint16_t));
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return bytes;
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}
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if (masked_addr >= 0x1f800000 && masked_addr < 0x1f800000 + 1024) {
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memcpy(&bytes, &scratchpad[masked_addr & 0x3ff], sizeof(uint16_t));
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return bytes;
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}
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if (masked_addr >= 0x00000000 && masked_addr < 0x00000000 + 0x200000) {
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memcpy(&bytes, &ram[masked_addr & 0x1fffff], sizeof(uint16_t));
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return bytes;
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}
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#ifdef ENABLE_RAM_MIRRORS
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if (masked_addr >= 0x00200000 && masked_addr < 0x00200000 + 0x200000) {
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memcpy(&bytes, &ram[masked_addr & 0x1fffff], sizeof(uint16_t));
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return bytes;
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}
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#endif
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if (masked_addr >= 0x1F000000 && masked_addr < 0x1F000000 + 0x400) {
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return 0xffff;
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}
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printf("\nUnhandled read 0x%.8x @ 0x%08x", masked_addr, pc);
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exit(0);
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}
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uint32_t memory::read32(uint32_t addr) {
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uint32_t bytes;
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uint32_t masked_addr = mask_address(addr);
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if (masked_addr == 0xfffffff8) return 0;
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/*if (masked_addr == 0xfffffff4) return 0;
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if (masked_addr == 0x00fffff4) return 0;
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if (masked_addr == 0x00fffff8) return 0;
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if (masked_addr == 0x00fffffc) return 0;*/
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// Timer 1 counter mode
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if (masked_addr == 0x1f801114) {
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printf("[TIMER] Read timer 1 counter mode (stubbed)\n");
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return 0;
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}
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if (masked_addr == 0x1f801014) return 0;
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if (masked_addr == 0x1f801060) { // RAM_SIZE
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return RAM_SIZE;
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}
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if (masked_addr == 0x1f802080) return 0x58534350; // "Also return 0x58534350 for 32-bit reads from 0x1f802080" - peach
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if (masked_addr == 0x1f801110) { // timer 1 stuff
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//printf("[TIMER] Read timer 1 current value\n");
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tmr1_stub += rand() % 4;
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return tmr1_stub;
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}
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if (masked_addr == 0x1f80101c) {
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return exp2_delay_size;
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}
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if (masked_addr == 0x1f801070) { // I_STAT
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return I_STAT;
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}
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if (masked_addr == 0x1f801074) { // I_MASK
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return I_MASK;
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}
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if (masked_addr == 0x1f801814) { // GPUSTAT
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if (debug) debug_log("\n GPUSTAT read");
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return 0b01011110100000000000000000000000; // stubbing it
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}
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if (masked_addr == 0x1f801810) { // GPUREAD
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return gpuread;
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}
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// dma
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if (masked_addr == 0x1f8010f0) // DCPR
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return DCPR;
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if (masked_addr == 0x1f8010f4) // DICR
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return DICR;
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// channel 1 (stubbed)
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if (masked_addr == 0x1f801090) { // base address
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printf("[DMA] Read DMA1 (mdec -> ram) base address (stubbed)\n");
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return 0;
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}
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if (masked_addr == 0x1f801094) { // block control
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printf("[DMA] Read DMA1 (mdec -> ram) block control (stubbed)\n");
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return 0;
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}
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if (masked_addr == 0x1f801098) { // control
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printf("[DMA] Read DMA1 (mdec -> ram) control (stubbed)\n");
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return 0;
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}
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// channel 2
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if (masked_addr == 0x1f8010a0) // base address
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return Ch2.MADR;
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if (masked_addr == 0x1f8010a4) // block control
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return Ch2.BCR;
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if (masked_addr == 0x1f8010a8) // control
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return Ch2.CHCR;
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// channel 3
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if (masked_addr == 0x1f8010b0) // base address
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return Ch3.MADR;
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if (masked_addr == 0x1f8010b4) // block control
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return Ch3.BCR;
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if (masked_addr == 0x1f8010b8) // control
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return Ch3.CHCR;
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// channel 6
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if (masked_addr == 0x1f8010e0) // base address
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return Ch6.MADR;
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if (masked_addr == 0x1f8010e4) // block control
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return Ch6.BCR;
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if (masked_addr == 0x1f8010e8) // control
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return Ch6.CHCR;
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if (masked_addr >= 0x1FC00000 && masked_addr < 0x1FC00000 + 524288) {
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memcpy(&bytes, &bios[masked_addr & 0x7ffff], sizeof(uint32_t));
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return bytes;
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}
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if (masked_addr >= 0x1f800000 && masked_addr < 0x1f800000 + 1024) {
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memcpy(&bytes, &scratchpad[masked_addr & 0x3ff], sizeof(uint32_t));
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return bytes;
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}
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if (masked_addr >= 0x00000000 && masked_addr < 0x00000000 + 0x200000) {
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memcpy(&bytes, &ram[masked_addr & 0x1fffff], sizeof(uint32_t));
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return bytes;
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}
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#ifdef ENABLE_RAM_MIRRORS
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if (masked_addr >= 0x00200000 && masked_addr < 0x00200000 + 0x200000) {
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memcpy(&bytes, &ram[masked_addr & 0x1fffff], sizeof(uint32_t));
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return bytes;
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}
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#endif
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// SPU
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if (masked_addr == 0x1F801D9C) {
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printf("[SPU] Read Voice 0..23 ON/OFF (stubbed)\n");
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return 0;
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}
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// MDEC
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if (masked_addr == 0x1f801820) {
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printf("[MDEC] Read MDEC Data/Response Register (stubbed)\n");
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return 0;
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}
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if (masked_addr == 0x1f801824) {
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printf("[MDEC] Read MDEC1 - MDEC Status Register (stubbed)\n");
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return 0;
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}
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if (masked_addr >= 0x1F000000 && masked_addr < 0x1F000000 + 0x400) {
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return 0xffffffff;
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}
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printf("\nUnhandled read 0x%.8x @ 0x%08x", masked_addr, pc);
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printf("\n$v0 is 0x%x\n", regs[2]);
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std::ofstream file("ram.bin", std::ios::binary);
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file.write((const char*)ram, 0x200000);
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debug_warn("Ram dumped.");
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exit(0);
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}
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void memory::write(uint32_t addr, uint8_t data, bool log) {
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uint32_t bytes;
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uint32_t masked_addr = mask_address(addr);
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// controllers
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if (masked_addr == 0x1f801040) {
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debug_warn("[PAD] Write 0x%x to JOY_TX_DATA\n", data);
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pads.WriteTXDATA(data);
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return;
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}
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if (masked_addr == 0x1f801800) { // cdrom status
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debug_log("[CDROM] Write 0x%x to status register\n", data);
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CDROM.status &= ~0b11;
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CDROM.status |= data & 0b11;
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return;
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}
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if (masked_addr == 0x1f801801) {
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switch (CDROM.status & 0b11) {
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case 0:
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CDROM.execute(data);
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break;
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case 3: break;
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default:
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printf("Unhandled CDROM write 0x%x index %d", addr, CDROM.status & 0b11);
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exit(0);
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}
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return;
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}
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if (masked_addr == 0x1f801802) {
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switch (CDROM.status & 0b11) {
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case 0:
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CDROM.push(data);
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break;
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case 1:
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debug_log("[CDROM] Write 0x%x to interrupt enable register\n", data);
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CDROM.interrupt_enable = data;
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break;
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case 2: printf("[CDROM] Write to Left-CD to Left-SPU Volume"); break;
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case 3: printf("[CDROM] Write to Right-CD to Left-SPU Volume\n"); break;
|
|
default:
|
|
printf("Unhandled CDROM write 0x%x index %d", addr, CDROM.status & 0b11);
|
|
exit(0);
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801803) {
|
|
switch (CDROM.status & 0b11) {
|
|
case 0:
|
|
debug_log("[CDROM] Write 0x%x to request register\n", data);
|
|
CDROM.request = data;
|
|
break;
|
|
case 1:
|
|
debug_log("[CDROM] Write 0x%x to interrupt flag register\n", data);
|
|
CDROM.interrupt_flag &= ~data;
|
|
if ((CDROM.interrupt_flag & 0b111) == 0) {
|
|
CDROM.irq = false;
|
|
}
|
|
break;
|
|
case 2: printf("[CDROM] Write to Left-CD to Right-SPU Volume\n"); break;
|
|
case 3: printf("[CDROM] Write to Audio Volume Apply Changes\n"); break;
|
|
default:
|
|
printf("Unhandled CDROM write 0x%x index %d", addr, CDROM.status & 0b11);
|
|
exit(0);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f802080) {
|
|
printf("%c", data);
|
|
logwnd->AddLog("%c", data);
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801104 || masked_addr == 0x1f801108 || masked_addr == 0x1f801100 || masked_addr == 0x1f801114 || masked_addr == 0x1f801118) {
|
|
////printf("[TIMER]] Write timer 0/1 regs (0x%08x)\n", masked_addr);
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f802041)
|
|
return;
|
|
|
|
if (masked_addr >= 0x1FC00000 && masked_addr < 0x1FC00000 + 0x7D000) {
|
|
printf("Attempted to overwrite bios!");
|
|
exit(0);
|
|
return;
|
|
}
|
|
|
|
if (masked_addr >= 0x1f800000 && masked_addr < 0x1f800000 + 1024) {
|
|
scratchpad[masked_addr & 0x3ff] = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr >= 0x00000000 && masked_addr < 0x00000000 + 0x200000) {
|
|
ram[masked_addr & 0x1fffff] = data;
|
|
return;
|
|
}
|
|
#ifdef ENABLE_RAM_MIRRORS
|
|
if (masked_addr >= 0x00200000 && masked_addr < 0x00200000 + 0x200000) {
|
|
ram[masked_addr & 0x1fffff] = data;
|
|
return;
|
|
}
|
|
#endif
|
|
if (masked_addr >= 0x1F000000 && masked_addr < 0x1F000000 + 0x400) {
|
|
exp1[masked_addr & 0xfffff] = data;
|
|
return;
|
|
}
|
|
|
|
else if (masked_addr == 0x1f802082) // exit code register for Continuous Integration tests
|
|
exit(data);
|
|
|
|
printf("\nUnhandled write 0x%.8x", masked_addr);
|
|
exit(0);
|
|
}
|
|
|
|
void memory::write32(uint32_t addr, uint32_t data) {
|
|
uint32_t bytes;
|
|
uint32_t masked_addr = mask_address(addr);
|
|
|
|
// if (masked_addr == 0x00fffffc) return;
|
|
|
|
if (masked_addr == 0x1f802084) { // Openbios stuff
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801060) { // RAM_SIZE
|
|
RAM_SIZE = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1F801070) { // I_STAT
|
|
debug_log("[IRQ] Write 0x%x to I_STAT\n", data);
|
|
I_STAT &= data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801074) { // I_MASK
|
|
I_MASK = data;
|
|
//if((I_MASK >> 6) & 1) CDROM.Scheduler.push(&TMR2IRQ, CDROM.Scheduler.time + 5000, this);
|
|
debug_log("[IRQ] Write 0x%x to I_MASK\n", data);
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f80101c) {
|
|
exp2_delay_size = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010f0) { // DCPR
|
|
DCPR = data;
|
|
if (debug) debug_log(" Write 0x%.8x to dcpr", data);
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010f4) { // DICR
|
|
DICR = data;
|
|
DICR &= ~(data & 0x7f000000);
|
|
if (debug) debug_log(" Write 0x%.8x to dicr", data);
|
|
return;
|
|
}
|
|
|
|
// channel 0 (stubbed)
|
|
if (masked_addr == 0x1f801080) { // base address
|
|
printf("[DMA] Write to DMA0 (ram -> mdec) base address (stubbed)\n");
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801084) { // block control
|
|
printf("[DMA] Write to DMA0 (ram -> mdec) block control (stubbed)\n");
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801088) { // control
|
|
printf("[DMA] Write to DMA0 (ram -> mdec) control (stubbed)\n");
|
|
return;
|
|
}
|
|
|
|
// channel 1 (stubbed)
|
|
if (masked_addr == 0x1f801090) { // base address
|
|
printf("[DMA] Write to DMA1 (mdec -> ram) base address (stubbed)\n");
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801094) { // block control
|
|
printf("[DMA] Write to DMA1 (mdec -> ram) block control (stubbed)\n");
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801098) { // control
|
|
printf("[DMA] Write to DMA1 (mdec -> ram) control (stubbed)\n");
|
|
return;
|
|
}
|
|
|
|
// channel 2
|
|
if (masked_addr == 0x1f8010a0) { // base address
|
|
Ch2.MADR = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010a4) { // block control
|
|
Ch2.BCR = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010a8) { // control
|
|
Ch2.CHCR = data;
|
|
return;
|
|
}
|
|
|
|
// channel 3
|
|
if (masked_addr == 0x1f8010b0) { // base address
|
|
Ch3.MADR = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010b4) { // block control
|
|
Ch3.BCR = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010b8) { // control
|
|
Ch3.CHCR = data;
|
|
return;
|
|
}
|
|
|
|
// channel 4
|
|
if (masked_addr == 0x1f8010c0) {
|
|
Ch4.MADR = data;
|
|
return;
|
|
}
|
|
if (masked_addr == 0x1f8010c4) {
|
|
Ch4.BCR = data;
|
|
return;
|
|
}
|
|
if (masked_addr == 0x1f8010c8) {
|
|
CDROM.Scheduler.push(&DMAIRQ, CDROM.Scheduler.time + 5000, this);
|
|
Ch4.CHCR = data;
|
|
return;
|
|
}
|
|
// channel 6
|
|
if (masked_addr == 0x1f8010e0) { // base address
|
|
Ch6.MADR = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010e4) { // block control
|
|
Ch6.BCR = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f8010e8) { // control
|
|
Ch6.CHCR = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801114) {
|
|
//////printf("[TIMER]] Sending TMR1 IRQ (stub)\n");
|
|
printf("[TIMER] Write timer 2 counter mode\n");
|
|
tmr1_stub = 0;
|
|
//CDROM.Scheduler.push(&TMR1IRQ, CDROM.Scheduler.time + 5000, this);
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801104 || masked_addr == 0x1f801108 || masked_addr == 0x1f801100 || masked_addr == 0x1f801114 || masked_addr == 0x1f801118) {
|
|
////printf("[TIMER]] Write timer 0/1 regs (0x%08x)\n", masked_addr);
|
|
return;
|
|
}
|
|
|
|
// MDEC
|
|
if (masked_addr == 0x1f801820) { // MDEC0 - MDEC Command/Parameter Register
|
|
printf("[MDEC] Write MDEC0 - MDEC Command/Parameter Register (0x%x) (stubbed)\n", data);
|
|
return;
|
|
}
|
|
if (masked_addr == 0x1f801824) { // MDEC1 - MDEC Control/Reset Register
|
|
printf("[MDEC] Write MDEC1 - MDEC Control/Reset Register (stubbed)\n");
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801814) return;
|
|
|
|
if (masked_addr == 0x1f801000) return; // Expansion 1 Base Address
|
|
if (masked_addr == 0x1f801004) return; // Expansion 2 Base Address
|
|
if (masked_addr == 0x1f801008) return; // Expansion 1 Delay/Size
|
|
if (masked_addr == 0x1f80100c) return; // Expansion 3 Delay/Size
|
|
if (masked_addr == 0x1f801010) return; // BIOS ROM Delay/Size
|
|
if (masked_addr == 0x1f801014) return; // SPU Delay/Size
|
|
if (masked_addr == 0x1f801018) return; // CDROM Delay/Size
|
|
if (masked_addr == 0x1f801020) return; // COM_DELAY / COMMON_DELAY
|
|
|
|
if (masked_addr >= 0xfffe0130 && masked_addr < 0xfffe0130 + sizeof(uint32_t)) { // CACHE_CONTROL
|
|
CACHE_CONTROL = data;
|
|
return;
|
|
}
|
|
write(addr, uint8_t(data & 0x000000ff), false);
|
|
write(addr + 3, uint8_t((data & 0xff000000) >> 24), false);
|
|
write(addr + 2, uint8_t((data & 0x00ff0000) >> 16), false);
|
|
write(addr + 1, uint8_t((data & 0x0000ff00) >> 8), false);
|
|
|
|
if (debug) debug_log(" Write 0x%.8x at address 0x%.8x", data, addr);
|
|
}
|
|
|
|
void memory::write16(uint32_t addr, uint16_t data) {
|
|
uint32_t masked_addr = mask_address(addr);
|
|
|
|
if (masked_addr == 0x1F801070) { // I_STAT
|
|
debug_log("[IRQ] Write 0x%x to I_STAT\n", data);
|
|
I_STAT &= data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1F801074) { // I_MASK
|
|
debug_log("[IRQ] Write 0x%x to I_MASK\n", data);
|
|
I_MASK = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f802082) // "its a PCSX register, ignore it"
|
|
return;
|
|
|
|
// controller
|
|
if (masked_addr == 0x1f80104a) {
|
|
debug_warn("[PAD] Write 0x%x to JOY_CTRL\n", data);
|
|
pads.joy_ctrl = data;
|
|
return;
|
|
}
|
|
if (masked_addr == 0x1f801048) {
|
|
debug_warn("[PAD] Write 0x%x to JOY_MODE\n", data);
|
|
pads.joy_mode = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f80104e) {
|
|
debug_warn("[PAD] Write 0x%x to JOY_BAUD\n", data);
|
|
pads.joy_baud = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801110) {
|
|
printf("[TIMER] Write timer 1 current value\n");
|
|
tmr1_stub = data;
|
|
return;
|
|
}
|
|
|
|
if (masked_addr == 0x1f801104 || masked_addr == 0x1f801108 || masked_addr == 0x1f801100 || masked_addr == 0x1f801114 || masked_addr == 0x1f801118 || masked_addr == 0x1f801110 || masked_addr == 0x1f801124 || masked_addr == masked_addr == 0x1f801124 || masked_addr == 0x1f801128 || masked_addr == 0x1f801120) {
|
|
printf("[TIMER] Write timer regs\n");
|
|
return;
|
|
}
|
|
|
|
if (masked_addr >= 0x1F801C00 && masked_addr <= 0x1F801E80) { // SPU regs
|
|
if (debug) debug_log(" SPU register write, ignored");
|
|
return;
|
|
}
|
|
|
|
write(addr, uint8_t(data & 0x00ff), false);
|
|
write(addr + 1, (data & 0xff00) >> 8, false);
|
|
|
|
if (debug) debug_log(" Write 0x%.4x at address 0x%.8x", read16(addr), addr);
|
|
}
|
|
|
|
|
|
static auto readBinary(std::string directory) -> std::vector<uint8_t> {
|
|
std::ifstream file(directory, std::ios::binary);
|
|
if (!file.is_open()) {
|
|
std::cout << "Couldn't find ROM at " << directory << "\n";
|
|
//exit(1);
|
|
}
|
|
|
|
std::vector<uint8_t> exe;
|
|
file.unsetf(std::ios::skipws);
|
|
std::streampos fileSize;
|
|
file.seekg(0, std::ios::end);
|
|
fileSize = file.tellg();
|
|
file.seekg(0, std::ios::beg);
|
|
|
|
exe.insert(exe.begin(),
|
|
std::istream_iterator<uint8_t>(file),
|
|
std::istream_iterator<uint8_t>());
|
|
file.close();
|
|
|
|
return exe;
|
|
}
|
|
|
|
#define MOD_ADLER 65521
|
|
// Taken from Wikipedia, used for the bios hash
|
|
uint32_t adler32(unsigned char* data, size_t len) {
|
|
uint32_t a = 1, b = 0;
|
|
size_t index;
|
|
|
|
// Process each byte of the data in order
|
|
for (index = 0; index < len; ++index)
|
|
{
|
|
a = (a + data[index]) % MOD_ADLER;
|
|
b = (b + a) % MOD_ADLER;
|
|
}
|
|
|
|
return (b << 16) | a;
|
|
}
|
|
|
|
void memory::loadBios(std::string directory) {
|
|
bios = readBinary(directory);
|
|
adler32bios = adler32(bios.data(), 0x80000);
|
|
printf("bios hash: 0x%x\n", adler32bios);
|
|
}
|
|
|
|
uint32_t memory::loadExec(std::string directory) {
|
|
file = readBinary(directory);
|
|
|
|
uint32_t start_pc;
|
|
uint32_t entry_addr;
|
|
uint32_t file_size;
|
|
|
|
memcpy(&start_pc, &file[0x10], sizeof(uint32_t));
|
|
memcpy(&entry_addr, &file[0x18], sizeof(uint32_t));
|
|
memcpy(&file_size, &file[0x1c], sizeof(uint32_t));
|
|
|
|
debug_log("\nStart pc: 0x%x", start_pc);
|
|
debug_log("\nDestination: 0x%x", entry_addr);
|
|
debug_log("\nFile size: 0x%x\n\n\n", file_size);
|
|
|
|
printf("%d, %d", file_size, file.size());
|
|
for (int i = 0; i < (file.size() - 2048); i++) {
|
|
write(entry_addr + i, file[0x800 + i], false);
|
|
}
|
|
|
|
return start_pc;
|
|
}
|
|
|
|
// HLE Syscalls
|
|
void memory::read_card_sector(int port, uint32_t sector, uint32_t dst) {
|
|
printf("read_card_sector:\nport: %d\nsector: %xh\n dst: %xh\n", port, sector, dst);
|
|
fseek(pads.memcard1, sector * 128, SEEK_SET);
|
|
uint8_t data[128];
|
|
fread(data, sizeof(uint8_t), 128, pads.memcard1);
|
|
for (int i = 0; i < 128; i++) {
|
|
write(dst + i, data[i], false);
|
|
}
|
|
} |