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https://github.com/ShadauxCat/CATSFC.git
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142 lines
4.1 KiB
C
142 lines
4.1 KiB
C
#ifndef _DS2_DMA_H__
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#define _DS2_DMA_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define MAX_DMA_NUM 6 /* max 6 channels */
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// DMA request source register
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#define DMAC_DRSR_RS_BIT 0
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#define DMAC_DRSR_RS_AUTO (8 << DMAC_DRSR_RS_BIT)
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// DMA channel command register
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#define DMAC_DCMD_SAI (1 << 23) /* source address increment */
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#define DMAC_DCMD_DAI (1 << 22) /* dest address increment */
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#define DMAC_DCMD_SWDH_BIT 14 /* source port width */
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#define DMAC_DCMD_SWDH_32 (0 << DMAC_DCMD_SWDH_BIT)
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#define DMAC_DCMD_SWDH_8 (1 << DMAC_DCMD_SWDH_BIT)
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#define DMAC_DCMD_SWDH_16 (2 << DMAC_DCMD_SWDH_BIT)
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#define DMAC_DCMD_DWDH_BIT 12 /* dest port width */
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#define DMAC_DCMD_DWDH_32 (0 << DMAC_DCMD_DWDH_BIT)
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#define DMAC_DCMD_DWDH_8 (1 << DMAC_DCMD_DWDH_BIT)
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#define DMAC_DCMD_DWDH_16 (2 << DMAC_DCMD_DWDH_BIT)
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#define DMAC_DCMD_DS_BIT 8 /* transfer data size of a data unit */
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#define DMAC_DCMD_DS_32BIT (0 << DMAC_DCMD_DS_BIT)
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#define DMAC_DCMD_DS_8BIT (1 << DMAC_DCMD_DS_BIT)
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#define DMAC_DCMD_DS_16BIT (2 << DMAC_DCMD_DS_BIT)
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#define DMAC_DCMD_DS_16BYTE (3 << DMAC_DCMD_DS_BIT)
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#define DMAC_DCMD_DS_32BYTE (4 << DMAC_DCMD_DS_BIT)
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#define DMAC_DCMD_TM (1 << 7) /* transfer mode: 0-single 1-block */
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//detect if channel has completed job
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#define DMAC_DCCSR_TT (1 << 3) /* transfer terminated */
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#define DMAC_BASE 0xB3020000
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#define REG32(addr) *((volatile u32 *)(addr))
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#define DMAC_DCCSR(n) (DMAC_BASE + (0x10 + (n) * 0x20)) /* DMA control/status */
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#define REG_DMAC_DCCSR(n) REG32(DMAC_DCCSR((n)))
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#define ds2_DMA_isBusy(n) \
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!( REG_DMAC_DCCSR((n)) & DMAC_DCCSR_TT )
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/*
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Copy modes
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*/
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#define DMA_MODE32BYTE DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_32BYTE | DMAC_DCMD_TM
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#define DMA_MODE16BYTE DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
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DMAC_DCMD_DS_16BYTE | DMAC_DCMD_TM
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#define DMA_MODE32BIT DMAC_DCMD_SWDH_32 | DMAC_DCMD_DWDH_32 | \
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DMAC_DCMD_DS_32BIT
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#define DMA_MODE16BIT DMAC_DCMD_SWDH_16 | DMAC_DCMD_DWDH_16 | \
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DMAC_DCMD_DS_16BIT
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#define DMA_MODE8BIT DMAC_DCMD_SWDH_8 | DMAC_DCMD_DWDH_8 | \
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DMAC_DCMD_DS_8BIT | DMAC_DCMD_TM
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#define DMA_MODECOPY DMAC_DCMD_SAI
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extern int _dmaCopy(int ch, void *dest, void *src, unsigned int size, unsigned int flags);
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/*
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* Copy 'size' bytes from src to dest, in blocks of 32 bytes.
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* size is in bytes and must be a multiple of 32.
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* Both src and dest must be aligned to 32 bytes.
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* Returns 0 on failure, non-zero on success.
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*/
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#define ds2_DMAcopy_32Byte(ch, dest, src, size)\
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_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE32BYTE)
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/*
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* Copy 'size' bytes from src to dest, in blocks of 16 bytes.
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* size is in bytes and must be a multiple of 16.
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* Both src and dest must be aligned to 16 bytes.
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* Returns 0 on failure, non-zero on success.
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*/
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#define ds2_DMAcopy_16Byte(ch, dest, src, size)\
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_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE16BYTE);
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/*
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* Copy 'size' bytes from src to dest, in blocks of 32 bits (4 bytes).
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* size is in bytes and must be a multiple of 4.
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* Both src and dest must be aligned to 32 bits (4 bytes).
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* Returns 0 on failure, non-zero on success.
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*/
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#define ds2_DMAcopy_32Bit(ch, dest, src, size)\
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_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE32BIT);
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/*
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* Copy 'size' bytes from src to dest, in blocks of 16 bits (2 bytes).
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* size is in bytes and must be a multiple of 2.
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* Both src and dest must be aligned to 16 bits (2 bytes).
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* Returns 0 on failure, non-zero on success.
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*/
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#define ds2_DMAcopy_16Bit(ch, dest, src, size)\
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_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE16BIT)
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/*
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* Copy 'size' individual bytes (8 bits at a time) from src to dest.
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* Returns 0 on failure, non-zero on success.
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*/
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#define ds2_DMAcopy_8Bit(ch, dest, src, size)\
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_dmaCopy(ch, dest, src, size, DMA_MODECOPY | DMA_MODE8BIT)
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//Stop DMA transfer
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extern void dma_stop(int ch);
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#define ds2_DMA_stop(ch)\
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dma_stop(ch)
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//Wait DMA transfer over
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extern int dma_wait_finish(int ch);
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#define ds2_DMA_wait(ch)\
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dma_wait_finish(ch)
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#ifdef __cplusplus
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}
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#endif
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#endif //__DMA_H__
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