3 commits

Author	SHA1	Message	Date
Nebuleon Fumika	e5869adc44	Merge Registers structures into their respective CPUs to avoid additional memory addresses being loaded every opcode.	2012-12-26 14:42:02 -05:00
Nebuleon Fumika	e708c127fa	Un-inline a bunch of stuff. ... With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached.	2012-12-18 22:53:49 -05:00
Kitty Draper	d40ae99422	first commit	2011-03-05 21:39:25 -05:00