Commit graph

9 commits

Author SHA1 Message Date
Nebuleon Fumika
1896286ad5 Permanently remove NO_OPEN_BUS hacks. It was a premature optimisation. 2013-01-08 16:26:43 -05:00
Nebuleon Fumika
bfef6f17bd Move some CPU cycle calculation from address resolution to the opcodes. This is to eventually move it from the resolved-address ops as well, reducing the number of memory stores. 2013-01-04 15:54:12 -05:00
Nebuleon Fumika
c5d385d664 MIPS requires 2-byte reads to be aligned to even addresses. #define FAST_ALIGNED_LSB_WORD_ACCESS and use it to read absolute 24-bit addresses as either 1 byte & 1 halfword, or 1 halfword & 1 byte. 2012-12-31 13:46:47 -05:00
Nebuleon Fumika
e5869adc44 Merge Registers structures into their respective CPUs to avoid additional memory addresses being loaded every opcode. 2012-12-26 14:42:02 -05:00
Nebuleon Fumika
f29c76dc58 End the use of global variables for CPU emulation. This creates fewer memory store instructions in many SNES, SA1 and APU opcodes.
Fix the APU half-carry bug, which may be audible.

globals.cpp: Get rid of A1, A2, A3, A4, W1, W2, W3, W4, Int8, Int16, Int32, Work8, Work16, Work32, Ans8, Ans16, Ans32.
2012-12-24 03:53:20 -05:00
Nebuleon Fumika
d1fe64aef0 Various optimisations in the CPU emulation.
Run the opcode as a tail call from the address calculation. This cuts on the needed return instructions.

Pass the opcode address as a parameter; this keeps it in a register most of the time and avoids memory stores.
2012-12-23 16:13:54 -05:00
Nebuleon Fumika
8085880130 Remove the SNES Open Bus behaviour by default. Also simplify translation again.
SNES Open Bus is a quirk of the memory subsystem that allow reads of invalid addresses to return the last byte read from memory. However, it is seldom needed by a game, and it costs 1 to 3 MIPS instructions per SNES instruction to emulate.

If you need SNES Open Bus, you can remove -DNO_OPEN_BUS from the Makefile.
2012-12-20 18:14:24 -05:00
Nebuleon Fumika
e708c127fa Un-inline a bunch of stuff.
With the MIPS instruction cache, this means that two consecutive SNES CPU instructions using e.g. the same addressing style or the same opcode have a chance that the second one will use the first one's code and that it will be cached.
2012-12-18 22:53:49 -05:00
Kitty Draper
d40ae99422 first commit 2011-03-05 21:39:25 -05:00