mirror of
https://github.com/daniel5151/ANESE.git
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307 lines
6.1 KiB
Text
Vendored
307 lines
6.1 KiB
Text
Vendored
//------------------------------- ::Opcodes:: --------------------------------//
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// Listed in the order that they should be checked
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/*==== Oddballs ====*/
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// Weird edge cases in the ISA
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// Need to be handled individually
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BRK 00 000 000 00 impl
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JSR 20 001 000 00 abs
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RTI 40 010 000 00 impl
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RTS 60 011 000 00 impl
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JMP 6c 011 011 00 ind // <-- the *only* indr instruction
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LDX be 101 111 10 abs,Y // grouped with abs,X
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STX 96 100 101 10 zpg,Y // grouped with zpg,X
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LDX b6 101 101 10 zpg,Y // grouped with zpg,X
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/*==== Conditional Branch Instructions ====*/
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// all have the form xxy10000
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//
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// i.e: (instr & 0x1F == 0x10)
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//
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// branch is taken if flag[xx] = y
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//
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// xx | flag
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// -------------
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// 00 | negative (N)
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// 01 | overflow (V)
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// 10 | carry (C)
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// 11 | zero (Z)
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//
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// so, all branch instructions can
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// be consolidated into one handler:
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//
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/**/ bool branch(u8 instr, u16 addr) {
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/**/ u8 xx = instr >> 6;
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/**/ bool y = instr & 0b00100000;
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/**/
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/**/ switch(xx) {
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/**/ case 0: return y == this->reg.p.n;
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/**/ case 1: return y == this->reg.p.v;
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/**/ case 2: return y == this->reg.p.c;
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/**/ case 3: return y == this->reg.p.z;
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/**/ }
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/**/
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/**/ assert(false);
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/**/ return false;
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/**/ }
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BPL 10 000 10000 rel
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BMI 30 001 10000 rel
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BVC 50 010 10000 rel
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BVS 70 011 10000 rel
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BCC 90 100 10000 rel
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BCS b0 101 10000 rel
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BNE d0 110 10000 rel
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BEQ f0 111 10000 rel
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/*==== Regular Instructions ====*/
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// cc = 00
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// aaa | op
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// ----|----
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// 000 | ...
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// 001 | BIT
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// 010 | JMP
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// 011 | ...
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// 100 | STY
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// 101 | LDY
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// 110 | CPY
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// 111 | CPX
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// bbb | addr mode
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// ----|-----------
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// 000 | #
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// 001 | zpg
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// 010 | impl
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// 011 | abs
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// 100 | rel
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// 101 | zpg,X
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// 110 | impl
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// 111 | abs,X
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// BPL 10 000 100 00 rel
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// BMI 30 001 100 00 rel
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// BVC 50 010 100 00 rel
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// BVS 70 011 100 00 rel
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// BCC 90 100 100 00 rel
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// BCS b0 101 100 00 rel
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// BNE d0 110 100 00 rel
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// BEQ f0 111 100 00 rel
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LDY a0 101 000 00 #
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CPY c0 110 000 00 #
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CPX e0 111 000 00 #
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BIT 24 001 001 00 zpg
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STY 84 100 001 00 zpg
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LDY a4 101 001 00 zpg
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CPY c4 110 001 00 zpg
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CPX e4 111 001 00 zpg
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PHP 08 000 010 00 impl
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PLP 28 001 010 00 impl
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PHA 48 010 010 00 impl
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PLA 68 011 010 00 impl
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DEY 88 100 010 00 impl
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TAY a8 101 010 00 impl
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INY c8 110 010 00 impl
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INX e8 111 010 00 impl
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BIT 2c 001 011 00 abs
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JMP 4c 010 011 00 abs
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// JMP 6c 011 011 00 ind
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STY 8c 100 011 00 abs
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LDY ac 101 011 00 abs
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CPY cc 110 011 00 abs
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CPX ec 111 011 00 abs
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STY 94 100 101 00 zpg,X
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LDY b4 101 101 00 zpg,X
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CLC 18 000 110 00 impl
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SEC 38 001 110 00 impl
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CLI 58 010 110 00 impl
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SEI 78 011 110 00 impl
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TYA 98 100 110 00 impl
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CLV b8 101 110 00 impl
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CLD d8 110 110 00 impl
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SED f8 111 110 00 impl
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LDY bc 101 111 00 abs,X
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// cc = 01
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// aaa | op
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// ----|-----
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// 000 | ORA
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// 001 | AND
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// 010 | EOR
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// 011 | ADC
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// 100 | STA
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// 101 | LDA
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// 110 | CMP
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// 111 | SBC
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// bbb | addr mode
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// ----|-----------
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// 000 | X,ind
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// 001 | zpg
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// 010 | #
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// 011 | abs
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// 100 | ind,Y
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// 101 | zpg,X
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// 110 | abs,Y
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// 111 | abs,X
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ORA 01 000 000 01 X,ind
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AND 21 001 000 01 X,ind
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EOR 41 010 000 01 X,ind
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ADC 61 011 000 01 X,ind
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STA 81 100 000 01 X,ind
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LDA a1 101 000 01 X,ind
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CMP c1 110 000 01 X,ind
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SBC e1 111 000 01 X,ind
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ORA 05 000 001 01 zpg
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AND 25 001 001 01 zpg
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EOR 45 010 001 01 zpg
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ADC 65 011 001 01 zpg
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STA 85 100 001 01 zpg
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LDA a5 101 001 01 zpg
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CMP c5 110 001 01 zpg
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SBC e5 111 001 01 zpg
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ORA 09 000 010 01 #
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AND 29 001 010 01 #
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EOR 49 010 010 01 #
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ADC 69 011 010 01 #
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// STA # is missing
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LDA a9 101 010 01 #
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CMP c9 110 010 01 #
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SBC e9 111 010 01 #
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ORA 0d 000 011 01 abs
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AND 2d 001 011 01 abs
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EOR 4d 010 011 01 abs
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ADC 6d 011 011 01 abs
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STA 8d 100 011 01 abs
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LDA ad 101 011 01 abs
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CMP cd 110 011 01 abs
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SBC ed 111 011 01 abs
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ORA 11 000 100 01 ind,Y
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AND 31 001 100 01 ind,Y
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EOR 51 010 100 01 ind,Y
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ADC 71 011 100 01 ind,Y
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STA 91 100 100 01 ind,Y
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LDA b1 101 100 01 ind,Y
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CMP d1 110 100 01 ind,Y
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SBC f1 111 100 01 ind,Y
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ORA 15 000 101 01 zpg,X
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AND 35 001 101 01 zpg,X
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EOR 55 010 101 01 zpg,X
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ADC 75 011 101 01 zpg,X
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STA 95 100 101 01 zpg,X
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LDA b5 101 101 01 zpg,X
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CMP d5 110 101 01 zpg,X
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SBC f5 111 101 01 zpg,X
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ORA 19 000 110 01 abs,Y
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AND 39 001 110 01 abs,Y
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EOR 59 010 110 01 abs,Y
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ADC 79 011 110 01 abs,Y
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STA 99 100 110 01 abs,Y
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LDA b9 101 110 01 abs,Y
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CMP d9 110 110 01 abs,Y
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SBC f9 111 110 01 abs,Y
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ORA 1d 000 111 01 abs,X
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AND 3d 001 111 01 abs,X
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EOR 5d 010 111 01 abs,X
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ADC 7d 011 111 01 abs,X
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STA 9d 100 111 01 abs,X
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LDA bd 101 111 01 abs,X
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CMP dd 110 111 01 abs,X
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SBC fd 111 111 01 abs,X
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// cc = 10
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// aaa | opcode
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// ----|-----
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// 000 | ASL
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// 001 | ROL
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// 010 | LSR
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// 011 | ROR
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// 100 | STX
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// 101 | LDX
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// 110 | DEC
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// 111 | INC
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// bbb | addr mode
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// ----|----------
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// 000 | #
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// 001 | zpg
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// 010 | A
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// 011 | abs
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// 100 |
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// 101 | zpg,X
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// 110 | impl
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// 111 | abs,X
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LDX a2 101 000 10 #
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ASL 06 000 001 10 zpg
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ROL 26 001 001 10 zpg
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LSR 46 010 001 10 zpg
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ROR 66 011 001 10 zpg
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STX 86 100 001 10 zpg
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LDX a6 101 001 10 zpg
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DEC c6 110 001 10 zpg
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INC e6 111 001 10 zpg
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ASL 0a 000 010 10 A
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ROL 2a 001 010 10 A
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LSR 4a 010 010 10 A
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ROR 6a 011 010 10 A
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// TXA 8a 100 010 10 impl
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// TAX aa 101 010 10 impl
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// DEX ca 110 010 10 impl
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// NOP ea 111 010 10 impl
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ASL 0e 000 011 10 abs
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ROL 2e 001 011 10 abs
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LSR 4e 010 011 10 abs
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ROR 6e 011 011 10 abs
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STX 8e 100 011 10 abs
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LDX ae 101 011 10 abs
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DEC ce 110 011 10 abs
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INC ee 111 011 10 abs
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ASL 16 000 101 10 zpg,X
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ROL 36 001 101 10 zpg,X
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LSR 56 010 101 10 zpg,X
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ROR 76 011 101 10 zpg,X
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// STX 96 100 101 10 zpg,Y
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// LDX b6 101 101 10 zpg,Y
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DEC d6 110 101 10 zpg,X
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INC f6 111 101 10 zpg,X
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TXS 9a 100 110 10 impl
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TSX ba 101 110 10 impl
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ASL 1e 000 111 10 abs,X
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ROL 3e 001 111 10 abs,X
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LSR 5e 010 111 10 abs,X
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ROR 7e 011 111 10 abs,X
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// LDX be 101 111 10 abs,Y
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DEC de 110 111 10 abs,X
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INC fe 111 111 10 abs,X
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// cc = 11
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// Doesn't exist!
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