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<TITLE>6502 Addressing Modes</TITLE>
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<H2>Addressing Modes</H2>
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<P>The 6502 processor provides several ways in which memory locations
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can be addressed. Some instructions support several different
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modes while others may only support one. In addition the two index
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registers can not always be used interchangeably. This lack of
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orthogonality in the instruction set is one of the features that
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makes the 6502 trickier to program well.</P>
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<H3><A NAME="IMP"></A>Implicit</H3>
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<P>For many 6502 instructions the source and destination of the
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information to be manipulated is implied directly by the function
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of the instruction itself and no further operand needs to be specified.
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Operations like 'Clear Carry Flag' (<A HREF="reference.html#CLC">CLC</A>)
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and 'Return from Subroutine' (<A HREF="reference.html#RTS">RTS</A>)
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are implicit.</P>
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<H3><A NAME="IMP"></A>Accumulator</H3>
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<P>Some instructions have an option to operate directly upon the
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accumulator. The programmer specifies this by using a special
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operand value, 'A'. For example:</P>
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<PRE> LSR A ;Logical shift right one bit
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ROR A ;Rotate right one bit</PRE>
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<H3><A NAME="IMM"></A>Immediate</H3>
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<P>Immediate addressing allows the programmer to directly specify
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an 8 bit constant within the instruction. It is indicated by a
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'#' symbol followed by an numeric expression. For example:</P>
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<PRE> LDA #10 ;Load 10 ($0A) into the accumulator
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LDX #LO LABEL ;Load the LSB of a 16 bit address into X
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LDY #HI LABEL ;Load the MSB of a 16 bit address into Y</PRE>
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<H3><A NAME="ZPG"></A>Zero Page</H3>
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<P>An instruction using zero page addressing mode has only an
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8 bit address operand. This limits it to addressing only the first
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256 bytes of memory (e.g. $0000 to $00FF) where the most significant
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byte of the address is always zero. In zero page mode only the
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least significant byte of the address is held in the instruction
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making it shorter by one byte (important for space saving) and
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one less memory fetch during execution (important for speed).</P>
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<P>An assembler will automatically select zero page addressing
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mode if the operand evaluates to a zero page address and the instruction
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supports the mode (not all do).</P>
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<PRE> LDA $00 ;Load accumulator from $00
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ASL ANSWER ;Shift labelled location ANSWER left</PRE>
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<H3><A NAME="ZPX"></A>Zero Page,X</H3>
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<P>The address to be accessed by an instruction using indexed
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zero page addressing is calculated by taking the 8 bit zero page
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address from the instruction and adding the current value of the
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X register to it. For example if the X register contains $0F and
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the instruction LDA $80,X is executed then the accumulator will
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be loaded from $008F (e.g. $80 + $0F => $8F).</P>
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<P><B>NB</B>:<BR>
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The address calculation wraps around if the sum of the base address
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and the register exceed $FF. If we repeat the last example but
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with $FF in the X register then the accumulator will be loaded
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from $007F (e.g. $80 + $FF => $7F) and not $017F.</P>
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<PRE> STY $10,X ;Save the Y register at location on zero page
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AND TEMP,X ;Logical AND accumulator with a zero page value</PRE>
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<H3><A NAME="ZPY"></A>Zero Page,Y</H3>
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<P>The address to be accessed by an instruction using indexed
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zero page addressing is calculated by taking the 8 bit zero page
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address from the instruction and adding the current value of the
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Y register to it. This mode can only be used with the <A HREF="reference.html#LDX">LDX</A>
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and <A HREF="reference.html#STX">STX</A> instructions.</P>
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<PRE> LDX $10,Y ;Load the X register from a location on zero page
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STX TEMP,Y ;Store the X register in a location on zero page</PRE>
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<H3><A NAME="REL"></A>Relative</H3>
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<P>Relative addressing mode is used by branch instructions (e.g.
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<A HREF="reference.html#BEQ">BEQ</A>, <A HREF="reference.html#BNE">BNE</A>,
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etc.) which contain a signed 8 bit relative offset (e.g. -128
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to +127) which is added to program counter if the condition is
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true. As the program counter itself is incremented during instruction
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execution by two the effective address range for the target instruction
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must be with -126 to +129 bytes of the branch.</P>
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<PRE> BEQ LABEL ;Branch if zero flag set to LABEL
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BNE *+4 ;Skip over the following 2 byte instruction</PRE>
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<H3><A NAME="ABS"></A>Absolute</H3>
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<P>Instructions using absolute addressing contain a full 16 bit
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address to identify the target location.</P>
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<PRE> JMP $1234 ;Jump to location $1234
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JSR WIBBLE ;Call subroutine WIBBLE</PRE>
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<H3><A NAME="ABX"></A>Absolute,X</H3>
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<P>The address to be accessed by an instruction using X register
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indexed absolute addressing is computed by taking the 16 bit address
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from the instruction and added the contents of the X register.
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For example if X contains $92 then an STA $2000,X instruction
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will store the accumulator at $2092 (e.g. $2000 + $92).</P>
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<PRE> STA $3000,X ;Store accumulator between $3000 and $30FF
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ROR CRC,X ;Rotate right one bit</PRE>
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<H3><A NAME="ABY"></A>Absolute,Y</H3>
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<P>The Y register indexed absolute addressing mode is the same
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as the previous mode only with the contents of the Y register
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added to the 16 bit address from the instruction.</P>
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<PRE> AND $4000,Y ;Perform a logical AND with a byte of memory
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STA MEM,Y ;Store accumulator in memory</PRE>
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<H3><A NAME="IND"></A>Indirect</H3>
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<P><A HREF="reference.html#JMP">JMP</A> is the only 6502 instruction
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to support indirection. The instruction contains a 16 bit address
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which identifies the location of the least significant byte of
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another 16 bit memory address which is the real target of the
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instruction.</P>
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<P>For example if location $0120 contains $FC and location $0121
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contains $BA then the instruction JMP ($0120) will cause the next
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instruction execution to occur at $BAFC (e.g. the contents of
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$0120 and $0121).</P>
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<PRE> JMP ($FFFC) ;Force a power on reset
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JMP (TARGET) ;Jump via a labelled memory area</PRE>
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<H3><A NAME="IDX"></A>Indexed Indirect</H3>
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<P>Indexed indirect addressing is normally used in conjunction with a table of address held on zero page. The address of the
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table is taken from the instruction and the X register added to
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it (with zero page wrap around) to give the location of the least
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significant byte of the target address.</P>
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<PRE> LDA ($40,X) ;Load a byte indirectly from memory
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STA (MEM,X) ;Store accumulator indirectly into memory</PRE>
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<H3><A NAME="IDY"></A>Indirect Indexed</H3>
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<P>Indirect indirect addressing is the most common indirection
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mode used on the 6502. In instruction contains the zero page location
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of the least significant byte of 16 bit address. The Y register
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is dynamically added to this value to generated the actual target
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address for operation.</P>
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<PRE> LDA ($40),Y ;Load a byte indirectly from memory
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STA (DST),Y ;Store accumulator indirectly into memory</PRE>
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<HR ALIGN=LEFT>This page was last updated on 28th December 2003
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