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28 lines
472 B
ArmAsm
28 lines
472 B
ArmAsm
; Synchronizes APU divide-by-two so that an STA $4017
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; immediately after the JSR (or some even number of
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; clocks after) will start the frame counter without
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; an extra clock delay.
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; Preserved: A, X, Y
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; Time: 16.7 msec
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sync_apu:
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pha
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; Clear IRQ flag
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sei
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lda #$40
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sta SNDMODE
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; Mode 0, frame IRQ enabled
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lda #$00
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sta SNDMODE
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delay 29825
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; Delay extra clock if odd alignment
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lda #$40
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bit SNDCHN
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bne :+
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:
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; Clear IRQ flag
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sta SNDMODE
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pla
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rts
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