mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
- Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/17496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
126 lines
2.5 KiB
Text
126 lines
2.5 KiB
Text
config SOC_INTEL_COMMON
|
|
bool
|
|
help
|
|
common code for Intel SOCs
|
|
|
|
if SOC_INTEL_COMMON
|
|
|
|
config CACHE_MRC_SETTINGS
|
|
bool "Save cached MRC settings"
|
|
default n
|
|
|
|
config SOC_INTEL_COMMON_SPI_FLASH_PROTECT
|
|
bool
|
|
default n
|
|
|
|
if CACHE_MRC_SETTINGS
|
|
|
|
config MRC_SETTINGS_CACHE_BASE
|
|
hex
|
|
default 0xfffe0000
|
|
|
|
config MRC_SETTINGS_CACHE_SIZE
|
|
hex
|
|
default 0x10000
|
|
|
|
config MRC_SETTINGS_PROTECT
|
|
bool "Enable protection on MRC settings"
|
|
default n
|
|
|
|
config HAS_RECOVERY_MRC_CACHE
|
|
bool
|
|
default n
|
|
|
|
config MRC_SETTINGS_VARIABLE_DATA
|
|
bool
|
|
default n
|
|
|
|
endif # CACHE_MRC_SETTINGS
|
|
|
|
config DISPLAY_MTRRS
|
|
bool "MTRRs: Display the MTRR settings"
|
|
default n
|
|
|
|
config DISPLAY_SMM_MEMORY_MAP
|
|
bool "SMM: Display the SMM memory map"
|
|
default n
|
|
|
|
config SOC_INTEL_COMMON_RESET
|
|
bool
|
|
default n
|
|
|
|
config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
|
|
bool
|
|
default n
|
|
|
|
config ACPI_CONSOLE
|
|
bool
|
|
default n
|
|
help
|
|
Provide a mechanism for serial console based ACPI debug.
|
|
|
|
config SOC_INTEL_COMMON_LPSS_I2C
|
|
bool
|
|
default n
|
|
help
|
|
This driver supports the Intel Low Power Subsystem (LPSS) I2C
|
|
controllers that are based on Synopsys DesignWare IP.
|
|
|
|
config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ
|
|
int
|
|
depends on SOC_INTEL_COMMON_LPSS_I2C
|
|
help
|
|
The clock speed that the I2C controller is running at, in MHz.
|
|
No default is set here as this is an SOC-specific value and must
|
|
be provided by the SOC when it selects this driver.
|
|
|
|
config SOC_INTEL_COMMON_LPSS_I2C_DEBUG
|
|
bool "Enable debug output for LPSS I2C transactions"
|
|
default n
|
|
depends on SOC_INTEL_COMMON_LPSS_I2C
|
|
help
|
|
Enable debug output for I2C transactions. This can be useful
|
|
when debugging I2C drivers.
|
|
|
|
config MMA
|
|
bool "Enable MMA (Memory Margin Analysis) support for Intel Core"
|
|
default n
|
|
depends on PLATFORM_USES_FSP2_0 || PLATFORM_USES_FSP1_1
|
|
help
|
|
Set this option to y to enable MMA (Memory Margin Analysis) support
|
|
|
|
config MMA_BLOBS_PATH
|
|
string "Path to MMA blobs"
|
|
depends on MMA
|
|
default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma"
|
|
|
|
config ADD_VBT_DATA_FILE
|
|
bool "Add a Video Bios Table (VBT) binary to CBFS"
|
|
help
|
|
Add a VBT file data file to CBFS. The VBT describes the integrated
|
|
GPU and connections, and is needed by FSP in order to initialize the
|
|
display.
|
|
|
|
config VBT_FILE
|
|
string "VBT binary path and filename"
|
|
depends on ADD_VBT_DATA_FILE
|
|
help
|
|
The path and filename of the VBT binary.
|
|
|
|
config SOC_INTEL_COMMON_GFX_OPREGION
|
|
bool
|
|
default n
|
|
|
|
config SOC_INTEL_COMMON_SMI
|
|
bool
|
|
default n
|
|
|
|
config SOC_INTEL_COMMON_ACPI
|
|
bool
|
|
default n
|
|
|
|
config SOC_INTEL_COMMON_NHLT
|
|
bool
|
|
default n
|
|
|
|
endif # SOC_INTEL_COMMON
|