mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
fd845a04a9
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
137 lines
2.9 KiB
C
137 lines
2.9 KiB
C
#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <pc80/mc146818rtc.h>
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#include "chip.h"
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#include "../southbridge/amd/cs5536/cs5536_smbus2.h"
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/* Borrowed from mc146818rtc.c */
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#define CMOS_READ(addr) ({ \
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outb((addr),RTC_PORT(0)); \
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inb(RTC_PORT(1)); \
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})
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#define CMOS_WRITE(val, addr) ({ \
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outb((addr),RTC_PORT(0)); \
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outb((val),RTC_PORT(1)); \
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})
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static void write_bit(unsigned char val) {
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unsigned char byte = CMOS_READ(440 / 8);
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/* Don't change it if its already set */
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if ((byte & 1) == (val & 1))
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return;
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byte &= ~1;
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byte |= val & 1;
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CMOS_WRITE(val, 440/8);
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}
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static unsigned short _getsmbusbase(void) {
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unsigned devfn = PCI_DEVFN(0xf, 0);
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device_t dev = dev_find_slot(0x0, devfn);
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unsigned long addr = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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return (unsigned short) (addr & ~1);
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}
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static void init_dcon(void) {
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int ret = 1;
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unsigned short rev = 0;
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unsigned short iobase = _getsmbusbase();
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printk_debug("CHECKING FOR DCON (%x)\n", iobase);
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/* Get the IO base for the SMBUS */
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rev = do_smbus_read_word(iobase, 0x0D << 1, 0x00);
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if (rev & 0xDC00) {
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printk_debug("DCON FOUND - REV %x\n", rev);
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/* Enable the DCON */
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ret = do_smbus_write_word(iobase, 0x0D << 1, 0x01, 0x0069);
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if (ret != 0)
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printk_debug("DCON ENABLE FAILED\n", ret);
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}
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else
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printk_debug("DCON NOT FOUND (%x)\n", rev);
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write_bit(rev > 0 ? 1 : 0);
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}
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void
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init_cafe_irq(void){
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const unsigned char slots_cafe[4] = {11, 0, 0, 0};
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/* CAFE PCI slots */
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pci_assign_irqs(0, 0x0C, slots_cafe);
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/* Make the pin assignments - NOTENOTENOTE: This should be
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* configurable!
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*/
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/* Configure the GPIO pins to use - class 0, index 9 to configure
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* AB. Write 0xFF to disable
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*/
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vrWrite(0x9, 0XFF00);
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/* Configure the GPIO pins to use - class 0, index A to configure
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* CD. Write 0xFF to disable
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*/
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vrWrite(0xA, 0xFFFF);
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}
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static void init(struct device *dev) {
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/*
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unsigned bus = 0;
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unsigned devfn = PCI_DEVFN(0xf, 4);
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device_t usb = NULL;
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unsigned char usbirq = 0xa;
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*/
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printk_debug("OLPC BTEST ENTER %s\n", __FUNCTION__);
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#if 0
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/* I can't think of any reason NOT to just set this. If it turns out we want this to be
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* conditional we can make it a config variable later.
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*/
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printk_debug("%s (%x,%x)SET USB PCI interrupt line to %d\n",
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__FUNCTION__, bus, devfn, usbirq);
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usb = dev_find_slot(bus, devfn);
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if (! usb){
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printk_err("Could not find USB\n");
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} else {
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pci_write_config8(usb, PCI_INTERRUPT_LINE, usbirq);
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}
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#endif
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init_dcon();
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init_cafe_irq();
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printk_debug("OLPC BTEST EXIT %s\n", __FUNCTION__);
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}
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static void enable_dev(struct device *dev)
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{
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dev->ops->init = init;
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}
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struct chip_operations mainboard_olpc_btest_ops = {
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CHIP_NAME("olpc btest mainboard ")
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.enable_dev = enable_dev,
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};
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