mirror of
https://github.com/fail0verflow/switch-coreboot.git
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fc56828763
BUG=None BRANCH=None TEST=None Change-Id: Ifb62bd0b5652d4533c7ccc5cc7c62e821a7e5db3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://chromium-review.googlesource.com/366262 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
59 lines
1.8 KiB
C
59 lines
1.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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static void sb700_enable_rom(void)
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{
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u32 word;
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u32 dword;
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pci_devfn_t dev;
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dev = PCI_DEV(0, 0x14, 0x03);
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/* SB700 LPC Bridge 0:20:3:44h.
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* BIT6: Port Enable for serial port 0x3f8-0x3ff
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* BIT29: Port Enable for KBC port 0x60 and 0x64
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* BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
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*/
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dword = pci_io_read_config32(dev, 0x44);
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//dword |= (1<<6) | (1<<29) | (1<<30) ;
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/*Turn on all of LPC IO Port decode enable */
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dword = 0xffffffff;
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pci_io_write_config32(dev, 0x44, dword);
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/* SB700 LPC Bridge 0:20:3:48h.
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* BIT0: Port Enable for SuperIO 0x2E-0x2F
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* BIT1: Port Enable for SuperIO 0x4E-0x4F
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* BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
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* BIT6: Port Enable for RTC IO 0x70-0x73
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* BIT21: Port Enable for Port 0x80
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*/
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dword = pci_io_read_config32(dev, 0x48);
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dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21) ;
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pci_io_write_config32(dev, 0x48, dword);
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/* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
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/* Set the 4MB enable bits */
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word = pci_io_read_config16(dev, 0x6c);
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word = 0xFFC0;
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pci_io_write_config16(dev, 0x6c, word);
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}
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static void bootblock_southbridge_init(void)
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{
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/* Setup the ROM access for 2M */
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sb700_enable_rom();
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}
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