Mohan D'Costa f9f53eb72f intel/minnowmax: Enable S3 suspend/resume ... This enables S3 Suspend / Resume support for MinnowMax board using Intel's Bay Trail FSP Tested resume from Power Button and Magic Packet. Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe Signed-off-by: Mohan D'Costa <mohan@ndr.co.jp> Reviewed-on: http://review.coreboot.org/6972 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins)		2014-09-29 19:36:29 +02:00
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arch	arm: Fix up new cache flush algorithm and replace dcache_*_all() with it	2014-09-29 17:26:45 +02:00
console	arm: Remove CAR_MIGRATE Kconfig and associated cruft	2014-09-15 17:38:28 +02:00
cpu	x86/mtrr: Enable MTRR's before enabling caching	2014-09-25 23:24:03 +02:00
device	Remove stale char[] initialization causing unaligned memory access	2014-09-29 19:26:49 +02:00
drivers	intel/fsp_baytrail: Add S3 suspend/resume Support	2014-09-29 19:35:57 +02:00
ec	google/chromeec: Notify DPTF charger participant on AC state change	2014-09-29 17:28:25 +02:00
include	Add check_member macro to allow clean and easy struct offset checking	2014-09-22 18:42:20 +02:00
lib	rmodule: Fix rmodule.ld for 64-bit	2014-09-23 22:27:10 +02:00
mainboard	intel/minnowmax: Enable S3 suspend/resume	2014-09-29 19:36:29 +02:00
northbridge	peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards	2014-09-25 18:33:28 +02:00
soc	intel/fsp_baytrail: Add S3 suspend/resume Support	2014-09-29 19:35:57 +02:00
southbridge	haswell: Move to per-device ACPI	2014-09-22 20:06:13 +02:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2014-09-17 17:34:16 +02:00
vendorcode	tpm: Clean up I2C TPM driver	2014-09-10 19:37:49 +02:00
Kconfig	coreboot arm64: Add support for arm64 into coreboot framework	2014-09-23 18:10:32 +02:00