mirror of
https://github.com/fail0verflow/switch-coreboot.git
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ff2ddcb313
This code has been tested on dbe62, and builds for qemu as well. the next step is testing on simnow. k8.h: add more prototypes and some required inline functions. cpu.h: same serengeti: expand defines in mainboard.h, though we need a better mechanism; continue to fix initram.c, add new support files to Makefile lib/console.c: include globalvars.h lib/lar.c: Provide more informative print as the lar is scanned. k8 north: needed reset_test.c from v2, fixes to raminit.c arch/x86 Kconfig: new CONFIG variable CBMEMK, meaning coreboot mem k, memory used for coreboot. init_cpus.c: functions to start up CPUs stage1_mtrr.c: bring over early mtrr support from v2. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@847 f3766cd6-281f-0410-b1cd-43a5c92072e9
219 lines
5.3 KiB
Text
219 lines
5.3 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config ARCH_X86
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boolean
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help
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This option is used to set the architecture of a mainboard.
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It is usually set in mainboard/*/Kconfig.
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config ARCH
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string
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default x86
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depends ARCH_X86
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help
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This is the name of the respective subdirectory in arch/.
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config CPU_I586
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_AMD_GEODELX
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CPU_AMD_K8
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boolean
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help
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CPU type. At the moment this option selects the reset vector and
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Cache-as-RAM (CAR) implementation for a mainboard. See
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arch/x86/Makefile for more hints on possible values.
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It is usually set in mainboard/*/Kconfig.
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config CONFIG_HPET
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boolean
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depends CPU_AMD_K8
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help
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Whether to configure a High Precision Event Timer. Note that HPETs are
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known to be bug-prone.
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config K8_REV_F_SUPPORT
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to include rev F support
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config K8_SCAN_PCI_BUS
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to scan the PCI bus in stage1
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config K8_ALLOCATE_IO_RANGE
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to allocate IO space in stage1
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config K8_ALLOCATE_MMIO_RANGE
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hex
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default 0 if CPU_AMD_K8
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help
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Whether to allocate MMIO space in stage1.
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Comment from code:
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Do we need allocate MMIO? Currently we direct
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last 64M to southbridge link (sblink) only,
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We can not lose access to last 4M range to ROM.
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config LOGICAL_CPUS
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hex
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depends CPU_AMD_K8
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default 1
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help
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How many logical CPUs there are. Fix me.
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config MAX_PHYSICAL_CPUS
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hex
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depends CPU_AMD_K8
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default 1
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help
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Max number of physical CPUs (sockets)
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config MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
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hex
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default 0 if CPU_AMD_K8
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help
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Config with 4 CPUs even if more are installed
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config CROSS_BAR_47_56
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hex
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default 0 if CPU_AMD_K8
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help
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Configure for the type of crossbar on the mainboard.
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config OPTION_TABLE
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boolean
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help
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This option is used to determine whether the mainboard has
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a battery backed up real time clock with CMOS NVRAM.
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It is usually set in mainboard/*/Kconfig.
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config PIRQ_TABLE
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boolean
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help
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This option is used to determine whether the mainboard has
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a PIRQ table, which is the old way to set up interrupt routing.
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It is usually set in mainboard/*/Kconfig.
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config ACPI_TABLE
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boolean
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help
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This option is used to determine whether the mainboard has
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an ACPI table.
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It is usually set in mainboard/*/Kconfig.
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config SMP
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boolean
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depends CPU_I586 || CPU_AMD_K8
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default 0
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help
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This option is used to enable certain functions to make
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coreboot work correctly on symmetric multi processor
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systems.
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It is usually set in mainboard/*/Kconfig.
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config IOAPIC
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boolean
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depends ARCH_X86 && CPU_AMD_K8
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default 0
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help
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If you want to configure an IOAPIC, set this.
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config CARBASE
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hex
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default 0x8f000 if CPU_I586
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default 0x80000 if CPU_AMD_GEODELX
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default 0xc8000 if CPU_AMD_K8
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help
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This option sets the base address of the area used for CAR.
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config CARSIZE
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hex
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default 0x1000 if CPU_I586
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default 0x8000 if CPU_AMD_GEODELX
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default 0x8000 if CPU_AMD_K8
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help
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This option sets the size of the area used for CAR.
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config CBMEMK
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hex
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default 0x1000 if CPU_I586
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default 0x1000 if CPU_AMD_GEODELX
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default 0x2000 if CPU_AMD_K8
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help
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This option sets the top of the memory area, in KiB,
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used for coreboot.
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config K8_HT_FREQ_1G_SUPPORT
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hex
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default 1 if CPU_AMD_K8
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help
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1 Ghz. support. Opteron E0 or later can support
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1G HT, but still depends on the mainboard
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config HT_FREQ_800MHZ
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hex
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default 1 if CPU_AMD_K8
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help
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Can we run HT at 800 Mhz
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config USBDEBUG_DIRECT
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boolean
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depends SOUTHBRIDGE_NVIDIA_MCP55
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default 0
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help
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Determines if we enable USB Direct debugging. If you don't have a dongle,
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this is probably of no value to you.
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config APIC_ID_OFFSET
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hex "APIC ID offset"
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default 0x10
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depends IOAPIC
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help
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This is entirely mainboard dependent. 0x10 is a *typical* setting but not always a good setting.
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menu "Debugging"
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config CARTEST
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bool "Test CAR area"
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default n
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help
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Test the CAR area after it has been set up.
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endmenu
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