mirror of
https://github.com/fail0verflow/switch-coreboot.git
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7f949f70f5
Phase 1: done Phase 2: early setup ... Phase 2: done Phase 3: Enumerating buses... qemu-x86 enable_dev done dev_phase3_scan: scanning Root Device scan_static_bus for root(Root Device) cpus: Unknown device path type: 0 cpus() enabled i440bxemulation_enable_dev: i440bxemulation_enable_dev: DONE northbridge_intel_i440bxemulation() enabled northbridge_intel_i440bxemulation() scanning... dev_phase3_scan: scanning pci_scan_bus start PCI: pci_scan_bus for bus 00 PCI: scan devfn 0x0 to 0xff PCI: devfn 0x0 PCI: pci_scan_bus pci_scan_get_dev returns dev <NULL> Change dts compiler to emit a new struct member, dtsname, for devices, so we can get actual useful names for things. Several mods and printks added. printk(BIOS_SPEW gives no output for reasons I don't understand. Next in line is bringing back v2 support for pci, but not doing it the way v2 does it. note the cpus() printk above. cpus don't have a valid path yet. We still need to work out the dts syntax for systems with multiple links (opteron) Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@163 f3766cd6-281f-0410-b1cd-43a5c92072e9
64 lines
2.1 KiB
Makefile
64 lines
2.1 KiB
Makefile
##
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## This file is part of the LinuxBIOS project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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#
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# VPD or SIP ROM or ... how does NVIDIA call it?
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# Some space to cope with dirty southbridge tricks.
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# Do we want to put our own stuff there, too?
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#
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$(obj)/linuxbios.vpd:
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$(Q)printf "Building dummy VPD... "
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$(Q)dd if=/dev/zero of=$(obj)/linuxbios.vpd bs=256 count=1 $(SILENT)
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$(Q)printf "done\n"
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#
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# This is going to be the init RAM code.
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#
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# The initram file is always uncompressed. It belongs into the mainboard
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# directory and is built from what was auto.c in v2.
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#
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$(obj)/linuxbios.initram: $(obj)/stage0.init $(obj)/stage0.o $(obj)/initram.o
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$(Q)printf "Building linuxbios.initram... "
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$(Q)# initram links against stage0
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$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x80000 $(obj)/initram.o \
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--entry=main -o $(obj)/linuxbios.initram.o
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$(Q)objcopy -O binary $(obj)/linuxbios.initram.o \
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$(obj)/linuxbios.initram
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$(Q)printf "done\n"
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#
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# Miscellaneous important targets.
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#
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$(obj)/mainboard.o: $(obj)/statictree.o
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$(obj)/statictree.o: $(obj)/statictree.c
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$(Q)$(CC) $(CFLAGS) $(LINUXBIOSINCLUDE) -c -o $(obj)/statictree.o $(obj)/statictree.c
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$(obj)/statictree.c: mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc
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$(Q)$(obj)/util/dtc/dtc -O lb mainboard/$(MAINBOARDDIR)/dts >$(obj)/statictree.c
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STAGE2_CHIPSET_OBJ =
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# chipset
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include $(src)/northbridge/intel/i440bxemulation/Makefile
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