Lee Leahy f45eb062da skylake: SPI code cleanup ... Move base address into iomap.h. Use PCI symbols instead of SPI specific symbols. Fix comments. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: Id5d21603150b52fd1b71dd448105938bd6aff1a9 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: http://review.coreboot.org/11826 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>		2015-10-11 23:57:53 +00:00
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acpi	acpi/sata: add generic sata ssdt port generator	2015-06-07 01:24:47 +02:00
arch	vboot: remove remnants of VBOOT_STUB	2015-10-11 23:55:50 +00:00
commonlib	vboot: prepare for x86 verstage	2015-10-11 23:57:29 +00:00
console	Add EM100 'hyper term' spi console support in ramstage & smm	2015-10-05 17:43:11 +00:00
cpu	arch/x86/bootblock: Do not include non-code files in bootblock.S	2015-10-08 19:11:24 +00:00
device	realmode/x86: Export vbe_mode_info_valid also in text mode.	2015-10-11 15:01:18 +00:00
drivers	intel fsp1_1: prepare for romstage vboot verification split	2015-10-11 23:55:45 +00:00
ec	chromeec: Fix ACPI compile warnings	2015-09-28 09:34:13 +00:00
include	cbmem console: make verstage first class citizen	2015-10-11 23:56:25 +00:00
lib	cbfs: don't load x86 programs over the top of read-only media	2015-10-11 23:56:46 +00:00
mainboard	intel fsp1_1: prepare for romstage vboot verification split	2015-10-11 23:55:45 +00:00
northbridge	Kill lvds_num_lanes	2015-10-11 10:07:17 +00:00
soc	skylake: SPI code cleanup	2015-10-11 23:57:53 +00:00
southbridge	x86/bootblock: Use LDFLAGS_bootblock to enable garbage collection	2015-10-07 03:08:58 +00:00
superio	superio/smsc: Add support for SMSC DME1737	2015-07-13 17:11:00 +02:00
vendorcode	vboot: prepare for x86 verstage	2015-10-11 23:57:29 +00:00
Kconfig	Kconfig: Hide RAM_CODE_SUPPORT.	2015-10-11 15:34:37 +00:00