mirror of
https://github.com/fail0verflow/switch-coreboot.git
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f222dfc6f5
Lots more to do. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1023 f3766cd6-281f-0410-b1cd-43a5c92072e9
234 lines
6 KiB
C
234 lines
6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <mainboard.h>
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#include <config.h>
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <cpu.h>
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#include <globalvars.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <mc146818rtc.h>
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#include <spd.h>
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#include "../../../northbridge/intel/i945/ich7.h"
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#include "../../../northbridge/intel/i945/i945.h"
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#define RC0 ((1<<0)<<8)
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#define DIMM0 0x50
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#define DIMM1 0x51
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/* this code is very mainboard dependent, sadly. */
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/**
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* no op at present
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*/
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static void memreset_setup(void)
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{
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}
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/**
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* this is a no op on this platform.
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*/
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void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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void activate_spd_rom(const struct mem_controller *ctrl)
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{
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}
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/**
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* read a byte from spd.
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* @param device device to read from
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* @param address address in the spd ROM
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* @return the value of the byte at that address.
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*/
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u8 spd_read_byte(u16 device, u8 address)
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{
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int do_smbus_read_byte(u16 device, u16 address);
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return do_smbus_read_byte(device, address);
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}
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static void early_ich7_init(void)
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{
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u8 reg8;
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u32 reg32;
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// program secondary mlt XXX byte?
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pci_conf1_write_config8(PCI_BDF(0, 0x1e, 0), 0x1b, 0x20);
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// reset rtc power status
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reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xa4);
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reg8 &= ~(1 << 2);
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pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xa4, reg8);
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// usb transient disconnect
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reg8 = pci_conf1_read_config8(PCI_BDF(0, 0x1f, 0), 0xad);
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reg8 |= (3 << 0);
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pci_conf1_write_config8(PCI_BDF(0, 0x1f, 0), 0xad, reg8);
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reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xfc);
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reg32 |= (1 << 29) | (1 << 17);
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pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xfc, reg32);
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reg32 = pci_conf1_read_config32(PCI_BDF(0, 0x1d, 7), 0xdc);
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reg32 |= (1 << 31) | (1 << 27);
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pci_conf1_write_config32(PCI_BDF(0, 0x1d, 7), 0xdc, reg32);
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RCBA32(0x0088) = 0x0011d000;
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RCBA16(0x01fc) = 0x060f;
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RCBA32(0x01f4) = 0x86000040;
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RCBA32(0x0214) = 0x10030549;
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RCBA32(0x0218) = 0x00020504;
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RCBA8(0x0220) = 0xc5;
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reg32 = RCBA32(0x3410);
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reg32 |= (1 << 6);
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RCBA32(0x3410) = reg32;
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reg32 = RCBA32(0x3430);
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reg32 &= ~(3 << 0);
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reg32 |= (1 << 0);
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RCBA32(0x3430) = reg32;
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RCBA32(0x3418) |= (1 << 0);
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RCBA16(0x0200) = 0x2008;
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RCBA8(0x2027) = 0x0d;
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RCBA16(0x3e08) |= (1 << 7);
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RCBA16(0x3e48) |= (1 << 7);
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RCBA32(0x3e0e) |= (1 << 7);
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RCBA32(0x3e4e) |= (1 << 7);
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// next step only on ich7m b0 and later:
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reg32 = RCBA32(0x2034);
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reg32 &= ~(0x0f << 16);
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reg32 |= (5 << 16);
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RCBA32(0x2034) = reg32;
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}
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static void rcba_config(void)
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{
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/* Set up virtual channel 0 */
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//RCBA32(0x0014) = 0x80000001;
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//RCBA32(0x001c) = 0x03128010;
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/* Device 1f interrupt pin register */
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RCBA32(0x3100) = 0x00042210;
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/* Device 1d interrupt pin register */
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RCBA32(0x310c) = 0x00214321;
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/* dev irq route register */
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RCBA16(0x3140) = 0x0132;
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RCBA16(0x3142) = 0x3241;
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RCBA16(0x3144) = 0x0237;
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RCBA16(0x3146) = 0x3210;
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RCBA16(0x3148) = 0x3210;
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/* Enable IOAPIC */
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RCBA8(0x31ff) = 0x03;
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/* Enable upper 128bytes of CMOS */
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RCBA32(0x3400) = (1 << 2);
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/* Disable unused devices */
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RCBA32(0x3418) = 0x000e0063;
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/* Enable PCIe Root Port Clock Gate */
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// RCBA32(0x341c) = 0x00000001;
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}
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/**
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* main for initram for the AMD DBM690T
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* @param init_detected Used to indicate that we have been started via init
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* @returns 0 on success
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* The purpose of this code is to not only get ram going, but get any other cpus/cores going.
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* The two activities are very tightly connected and not really seperable.
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*
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*/
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/*
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* init_detected is used to determine if we did a soft reset as required by a reprogramming of the
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* hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR.
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* That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset.
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* This value is picked up in assembly, or it should be.
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*/
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int main(void)
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{
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int boot_mode;
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void i945_early_initialization(void);
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void enable_smbus(void);
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int fixup_i945_errata(void);
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void i945_late_initialization(void);
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void sdram_initialize(int boot_mode);
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if (MCHBAR16(SSKPD) == 0xCAFE) {
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printk(BIOS_DEBUG, "soft reset detected.\n");
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boot_mode = 1;
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}
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/* Perform some early chipset initialization required
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* before RAM initialization can work
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*/
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i945_early_initialization();
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/* Enable SPD ROMs and DDR-II DRAM */
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enable_smbus();
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#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
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dump_spd_registers();
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#endif
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sdram_initialize(boot_mode);
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/* Perform some initialization that must run before stage2 */
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early_ich7_init();
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/* This should probably go away. Until now it is required
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* and mainboard specific
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*/
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rcba_config();
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/* Chipset Errata! */
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fixup_i945_errata();
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/* Initialize the internal PCIe links before we go into stage2 */
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i945_late_initialization();
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#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
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#if defined(DEBUG_RAM_SETUP)
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sdram_dump_mchbar_registers();
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#endif
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{
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/* This will not work if TSEG is in place! */
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u32 tom = pci_conf1_read_config32(PCI_BDF(0,2,0), 0x5c);
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printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom);
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ram_check(0x00000000, 0x000a0000);
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ram_check(0x00100000, tom);
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}
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#endif
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MCHBAR16(SSKPD) = 0xCAFE;
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}
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