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https://github.com/fail0verflow/switch-coreboot.git
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f1f8bc2cd4
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@367 f3766cd6-281f-0410-b1cd-43a5c92072e9
191 lines
4.2 KiB
C
191 lines
4.2 KiB
C
/*
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* This file is part of the LinuxBIOS project.
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*
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* It is based on the Linux kernel files include/asm-i386/processor.h
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* and arch/i386/kernel/cpu/mtrr/state.c.
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*
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* Modifications are:
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* Copyright (C) 2004 Linux Networx
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* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
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* Copyright (C) 2007 AMD
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* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*/
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#ifndef ARCH_X86_CPU_H
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#define ARCH_X86_CPU_H
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#include <types.h>
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/*
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* EFLAGS bits
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*/
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#define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
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#define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
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#define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
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#define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
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#define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
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#define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
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#define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
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#define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
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#define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
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#define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
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#define X86_EFLAGS_NT 0x00004000 /* Nested Task */
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#define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
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#define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
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#define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
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#define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
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#define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
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#define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
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struct cpuid_result {
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u32 eax;
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u32 ebx;
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u32 ecx;
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u32 edx;
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};
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/*
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* Generic CPUID function
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*/
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static inline struct cpuid_result cpuid(int op)
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{
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struct cpuid_result result;
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asm volatile(
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"cpuid"
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: "=a" (result.eax),
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"=b" (result.ebx),
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"=c" (result.ecx),
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"=d" (result.edx)
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: "0" (op));
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return result;
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}
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/*
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* CPUID functions returning a single datum
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*/
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static inline unsigned int cpuid_eax(unsigned int op)
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{
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unsigned int eax;
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__asm__("cpuid"
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: "=a" (eax)
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: "0" (op)
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: "ebx", "ecx", "edx");
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return eax;
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}
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static inline unsigned int cpuid_ebx(unsigned int op)
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{
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unsigned int eax, ebx;
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__asm__("cpuid"
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: "=a" (eax), "=b" (ebx)
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: "0" (op)
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: "ecx", "edx" );
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return ebx;
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}
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static inline unsigned int cpuid_ecx(unsigned int op)
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{
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unsigned int eax, ecx;
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__asm__("cpuid"
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: "=a" (eax), "=c" (ecx)
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: "0" (op)
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: "ebx", "edx" );
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return ecx;
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}
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static inline unsigned int cpuid_edx(unsigned int op)
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{
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unsigned int eax, edx;
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__asm__("cpuid"
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: "=a" (eax), "=d" (edx)
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: "0" (op)
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: "ebx", "ecx");
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return edx;
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}
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#define X86_VENDOR_INVALID 0
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#define X86_VENDOR_INTEL 1
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#define X86_VENDOR_CYRIX 2
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#define X86_VENDOR_AMD 3
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#define X86_VENDOR_UMC 4
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#define X86_VENDOR_NEXGEN 5
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#define X86_VENDOR_CENTAUR 6
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#define X86_VENDOR_RISE 7
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#define X86_VENDOR_TRANSMETA 8
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#define X86_VENDOR_NSC 9
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#define X86_VENDOR_SIS 10
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#define X86_VENDOR_UNKNOWN 0xff
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#include <device/device.h>
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struct cpu_info {
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struct device cpu;
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unsigned long index;
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};
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struct cpuinfo_x86 {
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u8 x86; /* CPU family */
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u8 x86_vendor; /* CPU vendor */
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u8 x86_model;
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u8 x86_mask;
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};
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/**
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* Get the u32 cpuinfo information into a struct cpuinfo.
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*/
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static void inline get_fms(struct cpuinfo_x86 *c, u32 tfms)
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{
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c->x86 = (tfms >> 8) & 0xf;
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c->x86_model = (tfms >> 4) & 0xf;
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c->x86_mask = tfms & 0xf;
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if (c->x86 == 0xf)
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c->x86 += (tfms >> 20) & 0xff;
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if (c->x86 >= 0x6)
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c->x86_model += ((tfms >> 16) & 0xF) << 4;
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}
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static inline unsigned long read_cr0(void)
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{
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unsigned long cr0;
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asm volatile ("movl %%cr0, %0" : "=r" (cr0));
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return cr0;
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}
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static inline void write_cr0(unsigned long cr0)
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{
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asm volatile ("movl %0, %%cr0" : : "r" (cr0));
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}
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static inline void invd(void)
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{
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asm volatile("invd" ::: "memory");
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}
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static inline void wbinvd(void)
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{
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asm volatile ("wbinvd");
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}
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static inline void enable_cache(void)
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{
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unsigned long cr0;
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cr0 = read_cr0();
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cr0 &= 0x9fffffff;
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write_cr0(cr0);
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}
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static inline void disable_cache(void)
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{
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/* Disable and write back the cache */
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unsigned long cr0;
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cr0 = read_cr0();
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cr0 |= 0x40000000;
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wbinvd();
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write_cr0(cr0);
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wbinvd();
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}
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#endif /* ARCH_X86_CPU_H */
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