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https://github.com/fail0verflow/switch-coreboot.git
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f1cf1f7c3a
rodata.pci_driver" warnings are coming from? We were packing those structures into a read-only segment, but forgot to mark them const. Despite its size, this is a fairly trivial patch created by a simple search/replace Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
137 lines
3.8 KiB
C
137 lines
3.8 KiB
C
/*
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* Copyright 2005 AMD
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* by yinghai.lu@amd.com
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pnp.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <pc80/mc146818rtc.h>
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#include <pc80/isa-dma.h>
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#include <bitops.h>
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#include <arch/io.h>
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#include "bcm5785.h"
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static void lpc_init(device_t dev)
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{
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/* Initialize the real time clock */
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rtc_init(0);
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/* Initialize isa dma */
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isa_dma_init();
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}
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static void bcm5785_lpc_read_resources(device_t dev)
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{
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struct resource *res;
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unsigned long index;
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/* Get the normal pci resources of this device */
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pci_dev_read_resources(dev);
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/* Add an extra subtractive resource for both memory and I/O */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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/**
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* @brief Enable resources for children devices
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*
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* @param dev the device whos children's resources are to be enabled
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*
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* This function is call by the global enable_resources() indirectly via the
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* device_operation::enable_resources() method of devices.
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*
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* Indirect mutual recursion:
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* enable_childrens_resources() -> enable_resources()
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* enable_resources() -> device_operation::enable_resources()
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* device_operation::enable_resources() -> enable_children_resources()
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*/
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static void bcm5785_lpc_enable_childrens_resources(device_t dev)
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{
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unsigned link;
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uint32_t reg;
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int i;
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int var_num = 0;
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reg = pci_read_config8(dev, 0x44);
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for (link = 0; link < dev->links; link++) {
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device_t child;
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for (child = dev->link[link].children; child; child = child->sibling) {
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enable_resources(child);
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if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) {
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for(i=0;i<child->resources;i++) {
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struct resource *res;
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unsigned long base, end; // don't need long long
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res = &child->resource[i];
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if(!(res->flags & IORESOURCE_IO)) continue;
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base = res->base;
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end = resource_end(res);
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printk_debug("bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
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switch(base) {
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case 0x60: //KBC
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case 0x64:
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reg |= (1<<29);
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case 0x3f8: // COM1
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reg |= (1<<6); break;
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case 0x2f8: // COM2
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reg |= (1<<7); break;
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case 0x378: // Parallal 1
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reg |= (1<<0); break;
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case 0x3f0: // FD0
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reg |= (1<<26); break;
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case 0x220: // Aduio 0
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reg |= (1<<14); break;
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case 0x300: // Midi 0
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reg |= (1<<18); break;
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}
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}
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}
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}
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}
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pci_write_config32(dev, 0x44, reg);
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}
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static void bcm5785_lpc_enable_resources(device_t dev)
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{
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pci_dev_enable_resources(dev);
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bcm5785_lpc_enable_childrens_resources(dev);
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}
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static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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pci_write_config32(dev, 0x40,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = lpci_set_subsystem,
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};
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static struct device_operations lpc_ops = {
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.read_resources = bcm5785_lpc_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = bcm5785_lpc_enable_resources,
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.init = lpc_init,
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.scan_bus = scan_static_bus,
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// .enable = bcm5785_enable,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver lpc_driver __pci_driver = {
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.ops = &lpc_ops,
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.vendor = PCI_VENDOR_ID_SERVERWORKS,
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.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_LPC,
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};
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