mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
e9352a13b2
Clean up the ASL whitespace and formatting to match the iasl -d style as other parts of coreboot. Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
36 lines
1.2 KiB
Text
36 lines
1.2 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Memory related values */
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Name (LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
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Name (PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
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Name (PBLN, 0x0) /* Length of BIOS area */
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/* Base address of PCIe config space */
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Name (PCBA, CONFIG_MMCONF_BASE_ADDRESS)
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/* Length of PCIe config space, 1MB each bus */
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Name (PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
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/* Base address of HPET table */
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Name (HPBA, 0xFED00000)
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/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
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Name (SSFG, 0x0D)
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/* Global Data */
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Name (OSVR, 3) /* WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
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Name (OSV, Ones) /* Assume nothing */
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Name (PMOD, One) /* Assume APIC */
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