mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
e7ff9d8839
Just took combined sandybridge per-device ACPI patch and applied it on FSP flavour to avoid need of separate tests. Change-Id: I09838cc01ede504416078edcb1c267a11539e714 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
87 lines
2.2 KiB
Text
87 lines
2.2 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 Google Inc.
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## Copyright (C) 2013 Sage Electronic Engineering, LLC.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config SOUTHBRIDGE_INTEL_FSP_BD82X6X
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bool
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if SOUTHBRIDGE_INTEL_FSP_BD82X6X
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config SOUTH_BRIDGE_OPTIONS # dummy
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def_bool y
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select IOAPIC
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select HAVE_HARD_RESET
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select HAVE_SMI_HANDLER
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select USE_WATCHDOG_ON_BOOT
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select PCIEXP_ASPM
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select PCIEXP_COMMON_CLOCK
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select SPI_FLASH
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select PER_DEVICE_ACPI_TABLES
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config EHCI_BAR
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hex
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default 0xfef00000
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config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "southbridge/intel/fsp_bd82x6x/bootblock.c"
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config SERIRQ_CONTINUOUS_MODE
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bool
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default n
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help
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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config HPET_MIN_TICKS
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hex
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default 0x80
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if HAVE_FSP_BIN
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config INCLUDE_ME
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bool
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default n
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help
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Include the me.bin and descriptor.bin for Intel PCH.
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This is usually required for the PCH.
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config ME_PATH
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string
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depends on INCLUDE_ME
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help
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The path of the ME and Descriptor files.
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config LOCK_MANAGEMENT_ENGINE
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bool "Lock Management Engine section"
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default n
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depends on INCLUDE_ME
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help
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The Intel Management Engine supports preventing write accesses
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from the host to the Management Engine section in the firmware
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descriptor. If the ME section is locked, it can only be overwritten
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with an external SPI flash programmer. You will want this if you
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want to increase security of your ROM image once you are sure
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that the ME firmware is no longer going to change.
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If unsure, say N.
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endif # HAVE_FSP_BIN
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endif
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