mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
6a732582c7
all stages, blighting everything with the same code, compiled different ways. In this change, we see that: - basic conf ops are compiled into stage0, where they are used. - they are called directly from initram - they are used to initialize the pci_cf8_conf1 structure in stage 2, but the call still goes to stage0! one copy of the code. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://coreboot.org/repository/coreboot-v3@752 f3766cd6-281f-0410-b1cd-43a5c92072e9
88 lines
2.5 KiB
C
88 lines
2.5 KiB
C
#include <console.h>
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#include <device/device.h>
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#include <pciconf.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <types.h>
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#include <io.h>
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const struct pci_bus_operations pci_cf8_conf1 = {
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.read8 = pci_conf1_read_config8,
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.read16 = pci_conf1_read_config16,
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.read32 = pci_conf1_read_config32,
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.write8 = pci_conf1_write_config8,
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.write16 = pci_conf1_write_config16,
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.write32 = pci_conf1_write_config32,
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.find = pci_conf1_find_device,
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};
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/*
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* Before we decide to use direct hardware access mechanisms, we try to do some
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* trivial checks to ensure it at least _seems_ to be working -- we just test
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* whether bus 00 contains a host bridge (this is similar to checking
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* techniques used in XFree86, but ours should be more reliable since we
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* attempt to make use of direct access hints provided by the PCI BIOS).
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*
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* This should be close to trivial, but it isn't, because there are buggy
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* chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
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*/
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static int pci_sanity_check(const struct pci_bus_operations *o)
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{
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u16 class, vendor;
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unsigned bus;
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int devfn;
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#define PCI_CLASS_BRIDGE_HOST 0x0600
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#define PCI_CLASS_DISPLAY_VGA 0x0300
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#define PCI_VENDOR_ID_COMPAQ 0x0e11
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#define PCI_VENDOR_ID_INTEL 0x8086
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#define PCI_VENDOR_ID_MOTOROLA 0x1057
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for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
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class = o->read16(PCI_BDEVFN(bus, devfn), PCI_CLASS_DEVICE);
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vendor = o->read16(PCI_BDEVFN(bus, devfn), PCI_VENDOR_ID);
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if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
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((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
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(vendor == PCI_VENDOR_ID_MOTOROLA))) {
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return 1;
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}
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}
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printk(BIOS_ERR, "PCI: Sanity check failed\n");
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return 0;
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}
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const struct pci_bus_operations *pci_check_direct(void)
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{
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unsigned int tmp;
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/*
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* Check if configuration type 1 works.
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*/
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{
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outb(0x01, 0xCFB);
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tmp = inl(0xCF8);
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outl(0x80000000, 0xCF8);
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if ((inl(0xCF8) == 0x80000000) &&
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pci_sanity_check(&pci_cf8_conf1))
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{
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outl(tmp, 0xCF8);
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printk(BIOS_DEBUG, "PCI: Using configuration type 1\n");
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return &pci_cf8_conf1;
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}
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outl(tmp, 0xCF8);
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}
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die("pci_check_direct failed\n");
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return NULL;
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}
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/** Set the method to be used for PCI, type I or type II
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*/
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void pci_set_method(struct device * dev)
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{
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printk(BIOS_INFO, "Finding PCI configuration type.\n");
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dev->ops->ops_pci_bus = pci_check_direct();
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post_code(POST_STAGE2_PHASE2_PCI_SET_METHOD);
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}
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