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https://github.com/fail0verflow/switch-coreboot.git
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e6e5b5ef55
Change-Id: I4cf0a67b0251d2d3adff5de74bf56b7d4c4524ee Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6811 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
161 lines
5.5 KiB
Text
161 lines
5.5 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/* Global Variables */
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Name(\PICM, 0) // IOAPIC/8259
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Name(\DSEN, 1) // Display Output Switching Enable
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/* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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*/
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External(NVSA)
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OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
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Field (GNVS, ByteAcc, NoLock, Preserve)
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{
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/* Miscellaneous */
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Offset (0x00),
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OSYS, 16, // 0x00 - Operating System
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SMIF, 8, // 0x02 - SMI function
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PRM0, 8, // 0x03 - SMI function parameter
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PRM1, 8, // 0x04 - SMI function parameter
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SCIF, 8, // 0x05 - SCI function
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PRM2, 8, // 0x06 - SCI function parameter
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PRM3, 8, // 0x07 - SCI function parameter
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LCKF, 8, // 0x08 - Global Lock function for EC
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PRM4, 8, // 0x09 - Lock function parameter
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PRM5, 8, // 0x0a - Lock function parameter
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P80D, 32, // 0x0b - Debug port (IO 0x80) value
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LIDS, 8, // 0x0f - LID state (open = 1)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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DBGS, 8, // 0x11 - Debug State
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LINX, 8, // 0x12 - Linux OS
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DCKN, 8, // 0x13 - PCIe docking state
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/* Thermal policy */
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Offset (0x14),
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ACTT, 8, // 0x14 - active trip point
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PSVT, 8, // 0x15 - passive trip point
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TC1V, 8, // 0x16 - passive trip point TC1
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TC2V, 8, // 0x17 - passive trip point TC2
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TSPV, 8, // 0x18 - passive trip point TSP
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CRTT, 8, // 0x19 - critical trip point
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DTSE, 8, // 0x1a - Digital Thermal Sensor enable
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DTS1, 8, // 0x1b - DT sensor 1
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DTS2, 8, // 0x1c - DT sensor 2
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/* Battery Support */
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Offset (0x1e),
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BNUM, 8, // 0x1e - number of batteries
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B0SC, 8, // 0x1f - BAT0 stored capacity
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B1SC, 8, // 0x20 - BAT1 stored capacity
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B2SC, 8, // 0x21 - BAT2 stored capacity
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B0SS, 8, // 0x22 - BAT0 stored status
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B1SS, 8, // 0x23 - BAT1 stored status
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B2SS, 8, // 0x24 - BAT2 stored status
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/* Processor Identification */
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Offset (0x28),
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APIC, 8, // 0x28 - APIC Enabled by coreboot
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MPEN, 8, // 0x29 - Multi Processor Enable
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PCP0, 8, // 0x2a - PDC CPU/CORE 0
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PCP1, 8, // 0x2b - PDC CPU/CORE 1
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PPCM, 8, // 0x2c - Max. PPC state
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/* Super I/O & CMOS config */
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Offset (0x32),
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NATP, 8, // 0x32 - ...
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/* Integrated Graphics Device */
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Offset (0x3c),
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IGDS, 8, // 0x3c - IGD state (primary = 1)
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TLST, 8, // 0x3d - Display Toggle List pointer
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CADL, 8, // 0x3e - Currently Attached Devices List
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PADL, 8, // 0x3f - Previously Attached Devices List
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CSTE, 16, // 0x40 - Current display state
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NSTE, 16, // 0x42 - Next display state
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SSTE, 16, // 0x44 - Set display state
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Offset (0x46),
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NDID, 8, // 0x46 - Number of Device IDs
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DID1, 32, // 0x47 - Device ID 1
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DID2, 32, // 0x4b - Device ID 2
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DID3, 32, // 0x4f - Device ID 3
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DID4, 32, // 0x53 - Device ID 4
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DID5, 32, // 0x57 - Device ID 5
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/* Backlight Control */
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Offset (0x64),
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BLCS, 8, // 0x64 - Backlight control possible?
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BRTL, 8, // 0x65 - Brightness Level
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ODDS, 8, // 0x66
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/* Ambient Light Sensors */
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Offset (0x6e),
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ALSE, 8, // 0x6e - ALS enable
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ALAF, 8, // 0x6f - Ambient light adjustment factor
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LLOW, 8, // 0x70 - LUX Low
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LHIH, 8, // 0x71 - LUX High
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/* EMA */
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Offset (0x78),
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EMAE, 8, // 0x78 - EMA enable
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EMAP, 16, // 0x79 - EMA pointer
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EMAL, 16, // 0x7b - EMA length
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/* MEF */
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Offset (0x82),
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MEFE, 8, // 0x82 - MEF enable
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/* TPM support */
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Offset (0x8c),
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TPMP, 8, // 0x8c - TPM
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TPME, 8, // 0x8d - TPM enable
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/* SATA */
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Offset (0x96),
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GTF0, 56, // 0x96 - GTF task file buffer for port 0
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GTF1, 56, // 0x9d - GTF task file buffer for port 1
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GTF2, 56, // 0xa4 - GTF task file buffer for port 2
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IDEM, 8, // 0xab - IDE mode (compatible / enhanced)
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IDET, 8, // 0xac - IDE
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/* IGD OpRegion */
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Offset (0xb4),
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ASLB, 32, // 0xb4 - IGD OpRegion Base Address
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IBTT, 8, // 0xb8 - IGD boot panel device
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IPAT, 8, // 0xb9 - IGD panel type cmos option
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ITVF, 8, // 0xba - IGD TV format cmos option
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ITVM, 8, // 0xbb - IGD TV minor format option
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IPSC, 8, // 0xbc - IGD panel scaling
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IBLC, 8, // 0xbd - IGD BLC config
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IBIA, 8, // 0xbe - IGD BIA config
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ISSC, 8, // 0xbf - IGD SSC config
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I409, 8, // 0xc0 - IGD 0409 modified settings
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I509, 8, // 0xc1 - IGD 0509 modified settings
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I609, 8, // 0xc2 - IGD 0609 modified settings
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I709, 8, // 0xc3 - IGD 0709 modified settings
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IDMM, 8, // 0xc4 - IGD DVMT Mode
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IDMS, 8, // 0xc5 - IGD DVMT memory size
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IF1E, 8, // 0xc6 - IGD function 1 enable
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HVCO, 8, // 0xc7 - IGD HPLL VCO
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NXD1, 32, // 0xc8 - IGD _DGS next DID1
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NXD2, 32, // 0xcc - IGD _DGS next DID2
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NXD3, 32, // 0xd0 - IGD _DGS next DID3
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NXD4, 32, // 0xd4 - IGD _DGS next DID4
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NXD5, 32, // 0xd8 - IGD _DGS next DID5
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NXD6, 32, // 0xdc - IGD _DGS next DID6
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NXD7, 32, // 0xe0 - IGD _DGS next DID7
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NXD8, 32, // 0xe4 - IGD _DGS next DID8
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/* Mainboard Specific (TODO move elsewhere) */
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Offset (0xf0),
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DOCK, 8, // 0xf0 - Docking Status
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}
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