switch-coreboot/src
Martin Roth e6df041b8b mainboard/intel/minnowmax: Add MinnowMax mainboard
MinnowMax board using Intel's Bay Trail FSP

Working:
- Booting from SATA / USB / (USB3 with latest SeaBIOS)

Not working:
- Boot from SD
- S3 Suspend / Resume

***** To configure the FSP *****
Download the Bay Trail FSP and the binary config tool:

Modify the standard Bay Trail FSP:
run the bct tool with the command line options:
bct --bin <Bay Trail FSP Binary> \
	--absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \
	--bout <path to save the updated FSP to>

Here are the required changes for modifying the FSP manually:
	Enable Memory Down: Enabled
	DRAM Speed: 1066 MHz
	DIMM_DWidth: x16
	DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max)
	tCL: 7
	tRP_tRCD: 7
	tWR: 8
	tRRD: 6
	tRTP: 4
	tFAW: 27
Other FSP values can remain the same.

***** To configure the vbios *****
The vbios is in the Bay Trail FSP package.
Download Intel's "Binary Modification Program" (BMP)
Use it to disable all ports except HDMI on port B.

Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6429
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11 19:01:25 +02:00
..
arch coreboot classes: Add dynamic classes to coreboot 2014-08-11 15:42:20 +02:00
console src/console/Kconfig: Fix choice for showing POST codes on console 2014-07-30 20:34:08 +02:00
cpu x86/smm/smihandler.c: break case in switch 2014-08-11 17:03:45 +02:00
device device/oprom/realmode: Sanitize header inclusion 2014-08-08 03:32:13 +02:00
drivers drivers: Add I2C TPM driver to coreboot 2014-08-10 22:25:48 +02:00
ec lenovo/h8: Remove useless smi.h include. 2014-08-11 00:46:33 +02:00
include coreboot_tables: reduce redundant data structures 2014-08-10 22:23:19 +02:00
lib coreboot classes: Add dynamic classes to coreboot 2014-08-11 15:42:20 +02:00
mainboard mainboard/intel/minnowmax: Add MinnowMax mainboard 2014-08-11 19:01:25 +02:00
northbridge northbridge/intel/*/gma.c: Remove dead code 2014-08-11 16:12:07 +02:00
soc soc/intel/fsp_baytrail: set up for including irqroute.h twice 2014-08-11 07:22:58 +02:00
southbridge i82801ix: Declare gen decode registers. 2014-08-11 09:12:29 +02:00
superio superio/smsc/sio1036: Clean up RAMstage superio.c component 2014-08-09 10:06:13 +02:00
vendorcode coreboot classes: Add dynamic classes to coreboot 2014-08-11 15:42:20 +02:00
Kconfig drivers: Add I2C TPM driver to coreboot 2014-08-10 22:25:48 +02:00