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https://github.com/fail0verflow/switch-coreboot.git
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4110e67004
Continue to upgrade northbridge for k8. Add a new standard include (which is optional on some chipsets), mainboard.h, which will define important mainboard constants that 1. do not belong in dts 2. do not belong in Kconfig 3. are so tightly tied down to the mainboard they should probably not be visible, i.e. the value of the variable is defined by artwork on the mainboard, such as the socket type. This file resolves the long-standing question of where certain mainboard-dependent, compile-time control variables belong. We've not resolved this issue in two years so here's how we're going to do it. The first use of this is in the definition of CPU_SOCKET_TYPE, needed by the northbridge code. These changes do not affect existing Geode builds (tested on DBE62). Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@792 f3766cd6-281f-0410-b1cd-43a5c92072e9
88 lines
3.4 KiB
C
88 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* SPDs for DDR2 SDRAM */
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#define SPD_MEM_TYPE 2
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#define SPD_MEM_TYPE_SDRAM_DDR 0x07
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#define SPD_MEM_TYPE_SDRAM_DDR2 0x08
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#define SPD_DIMM_TYPE 20 /* x bit0 or bit4 =1 mean registered*/
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#define SPD_DIMM_TYPE_RDIMM (1<<0)
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#define SPD_DIMM_TYPE_UDIMM (1<<1)
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#define SPD_DIMM_TYPE_SODIMM (1<<2)
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#define SPD_DIMM_TYPE_uDIMM (1<<3)
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#define SPD_DIMM_TYPE_mRDIMM (1<<4)
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#define SPD_DIMM_TYPE_mUDIMM (1<<5)
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#define SPD_MOD_ATTRIB 21
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#define SPD_MOD_ATTRIB_DIFCK 0x20
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#define SPD_MOD_ATTRIB_REGADC 0x11 /* x */
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#define SPD_MOD_ATTRIB_PROBE 0x40
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#define SPD_DEV_ATTRIB 22 /* Device attributes --- general */
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#define SPD_DIMM_CONF_TYPE 11
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#define SPD_DIMM_CONF_TYPE_ECC 0x02
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#define SPD_DIMM_CONF_TYPE_ADDR_PARITY 0x04 /* ? */
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#define SPD_ROW_NUM 3 /* Number of Row addresses */
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#define SPD_COL_NUM 4 /* Number of Column addresses */
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#define SPD_BANK_NUM 17 /* SDRAM Device attributes - Number of Banks on
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SDRAM device, it could be 0x4, 0x8, so address
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lines for that would be 2, and 3 */
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/* Number of Ranks bit [2:0], Package (bit4, 1=stack, 0=planr), Height bit[7:5] */
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#define SPD_MOD_ATTRIB_RANK 5
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#define SPD_MOD_ATTRIB_RANK_NUM_SHIFT 0
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#define SPD_MOD_ATTRIB_RANK_NUM_MASK 0x07
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#define SPD_MOD_ATTRIB_RANK_NUM_BASE 1
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#define SPD_MOD_ATTRIB_RANK_NUM_MIN 1
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#define SPD_MOD_ATTRIB_RANK_NUM_MAX 8
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#define SPD_RANK_SIZE 31 /* Only one bit is set */
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#define SPD_RANK_SIZE_1GB (1<<0)
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#define SPD_RANK_SIZE_2GB (1<<1)
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#define SPD_RANK_SIZE_4GB (1<<2)
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#define SPD_RANK_SIZE_8GB (1<<3)
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#define SPD_RANK_SIZE_16GB (1<<4)
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#define SPD_RANK_SIZE_128MB (1<<5)
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#define SPD_RANK_SIZE_256MB (1<<6)
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#define SPD_RANK_SIZE_512MB (1<<7)
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#define SPD_DATA_WIDTH 6 /* valid value 0, 32, 33, 36, 64, 72, 80, 128, 144, 254, 255 */
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#define SPD_PRI_WIDTH 13 /* Primary SDRAM Width, it could be 0x08 or 0x10 */
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#define SPD_ERR_WIDTH 14 /* Error Checking SDRAM Width, it could be 0x08 or 0x10 */
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#define SPD_CAS_LAT 18 /* SDRAM Device Attributes -- CAS Latency */
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#define SPD_CAS_LAT_2 (1<<2)
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#define SPD_CAS_LAT_3 (1<<3)
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#define SPD_CAS_LAT_4 (1<<4)
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#define SPD_CAS_LAT_5 (1<<5)
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#define SPD_CAS_LAT_6 (1<<6)
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#define SPD_TRP 27 /* bit [7:2] = 1-63 ns, bit [1:0] 0.25ns+, final value ((val>>2) + (val & 3) * 0.25)ns */
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#define SPD_TRRD 28
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#define SPD_TRCD 29
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#define SPD_TRAS 30
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#define SPD_TWR 36 /* x */
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#define SPD_TWTR 37 /* x */
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#define SPD_TRTP 38 /* x */
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#define SPD_TRC 41 /* add byte 0x40 bit [3:1] , so final val41+ table[((val40>>1) & 0x7)] ... table[]={0, 0.25, 0.33, 0.5, 0.75, 0, 0}*/
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#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/
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#define SPD_TREF 12
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