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https://github.com/fail0verflow/switch-coreboot.git
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e3abcbefc2
affected. This mostly targets pci_*_config*() calls. This is part of my quest to make existing code more readable without looking up the meaning of magic numbers. Ron pointed out that this enables better kscope usage. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@913 f3766cd6-281f-0410-b1cd-43a5c92072e9
83 lines
2.7 KiB
C
83 lines
2.7 KiB
C
/*
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*
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* This file is part of the coreboot project.
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* Copyright (C) 2003 Linux Networx
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "amd8111.h"
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static void pci_init(struct device *dev)
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{
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/* Enable pci error detecting */
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u32 dword;
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/* System error enable */
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dword = pci_read_config32(dev, PCI_COMMAND);
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dword |= (1<<8); /* System error enable */
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dword |= (7<<28); /* Clear possible errors */
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pci_write_config32(dev, PCI_COMMAND, dword);
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/* System,Parity,timer,and abort error enable */
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dword = pci_read_config32(dev, 0x3c);
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dword |= (1<<16); /* Parity */
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dword |= (1<<17); /* System */
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dword |= (1<<21); /* Master abort */
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// dword &= ~(1<<21); /* Master abort */
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// dword |= (1<<27); /* Discard timer */
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dword &= ~(1<<27); /* Discard timer */
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dword |= (1<<26); /* DTSTAT error clear */
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pci_write_config32(dev, 0x3c, dword);
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/* CRC flood enable */
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dword = pci_read_config32(dev, 0xc4);
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dword |= (1<<1); /* CRC Flood enable */
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dword |= (1<<8); /* Clear any CRC errors */
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dword |= (1<<4); /* Clear any LKFAIL errors */
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pci_write_config32(dev, 0xc4, dword);
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/* Clear possible errors */
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dword = pci_read_config32(dev, 0x1c);
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dword |= (1<<27); /* STA */
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dword |= (1<<28); /* RTA */
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dword |= (1<<29); /* RMA */
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dword |= (1<<30); /* RSE */
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dword |= (1<<31); /* DPE */
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dword |= (1<<24); /* MDPE */
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pci_write_config32(dev, 0x1c, dword);
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}
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struct device_operations amd8111_pci = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_8111_PCI}}},
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.constructor = default_device_constructor,
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.phase3_scan = pci_scan_bridge,
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.phase4_enable_disable = amd8111_enable,
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.phase4_read_resources = pci_bus_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_bus_enable_resources,
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.phase6_init = pci_init,
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};
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