mirror of
https://github.com/fail0verflow/switch-coreboot.git
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e3517187a0
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@911 f3766cd6-281f-0410-b1cd-43a5c92072e9
79 lines
2.3 KiB
C
79 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/pci.h>
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#include <msr.h>
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#include <legacy.h>
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#include <device/pci_ids.h>
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#include <statictree.h>
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#include <config.h>
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#include "sb600.h"
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static void ide_init(struct device *dev)
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{
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struct southbridge_amd_sb600_ide_dts_config *conf;
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/* Enable ide devices so the linux ide driver will work */
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u32 dword;
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u8 byte;
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conf = dev->device_configuration;
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/* RPR10.1 disable MSI */
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dword = pci_read_config32(dev, 0x70);
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dword &= ~(1 << 16);
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pci_write_config32(dev, 0x70, dword);
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/* Ultra DMA mode */
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byte = pci_read_config8(dev, 0x54);
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byte |= 1 << 0;
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pci_write_config8(dev, 0x54, byte);
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byte = pci_read_config8(dev, 0x56);
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byte &= ~(7 << 0);
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byte |= 5 << 0; /* mode 5 */
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pci_write_config8(dev, 0x56, byte);
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/* Enable I/O Access&& Bus Master */
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dword = pci_read_config16(dev, 0x4);
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dword |= 1 << 2;
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pci_write_config16(dev, 0x4, dword);
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#if CONFIG_PCI_OPTION_ROM_RUN == 1
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pci_dev_init(dev);
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#endif
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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struct device_operations sb600_ide = {
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.id = {.type = DEVICE_ID_PCI,
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{.pci = {.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_ATI_SB600_IDE}}},
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.constructor = default_device_constructor,
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.phase4_enable_disable = sb600_enable,
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.phase4_read_resources = pci_dev_read_resources,
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.phase4_set_resources = pci_dev_set_resources,
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.phase5_enable_resources = pci_dev_enable_resources,
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.phase6_init = ide_init,
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.ops_pci = &lops_pci
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};
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