mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
- p4dpe sync with LNXI tree * Make switching to fallback mode more robust Added boot_countdown to count the number of times booting has failed. * Added boot index to allow fully forcing the boot device with cmos options * Added missing irqs to the mptable. - p4dpr sync with LNXI tree * Make switching to fallback mode more robust Added boot_countdown to count the number of times booting has failed. * Added boot index to allow fully forcing the boot device with cmos options - tyan/guiness repair and update the Config file - northbridge/amd/amd76x/ * Support for up to 4GB of ram. * Correct handling of strange dimm sizes - northbridge/intel/E7500 * Tunned settings for better memory performance - northbridge/intel/E7501 * Fixed calculations based on a 100Mhz to use a 133Mhz clock. * Replaced hard codes for the supermicro x5dpr * Misc bug fixes - src/ram/spotcheck.inc * Removed someones temporary debugging code - src/sdram/generci_zero_ecc_sdram.inc * Handle addresses > 2GB - src/southbridge/amd/amd768/ * Changed references to the amd766 to the amd768 * misc fixes * Added a count to the failover code so we trigger fallback much less easily. * more attempts to disable the amd768 watchdog... * reset the board on a timeout reading from the smbus. - src/southbridge/intel/82801 * added a count of boot failers so we trigger fallback mode much leass easily. - Added motherboards p4dpeg2, x5dpr, s2466, s2469 |
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.. | ||
Config | ||
dump_northbridge.inc | ||
dump_northbridge2.inc | ||
ramtest.c | ||
ramtest.inc | ||
spotcheck.inc |