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https://github.com/fail0verflow/switch-coreboot.git
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6220b632e7
- I left LB_TAG_ intact because they are used by the payloads - file renames are still missing. see next commit - some lb_ renames might be missing. feel free to provide patches. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
45 lines
1.5 KiB
Makefile
45 lines
1.5 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
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#
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# This is going to be the init RAM code.
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#
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# The initram file is always uncompressed. It belongs into the mainboard
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# directory and is built from what was auto.c in v2.
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#
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INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
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$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
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STAGE2_MAINBOARD_OBJ = vga.o
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#
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# VPD or SIP ROM or... how does NVIDIA call it?
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# Some space to cope with dirty southbridge tricks.
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# Do we want to put our own stuff there, too?
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#
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$(obj)/coreboot.vpd:
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$(Q)printf " BUILD DUMMY VPD\n"
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$(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT)
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