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https://github.com/fail0verflow/switch-coreboot.git
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6220b632e7
- I left LB_TAG_ intact because they are used by the payloads - file renames are still missing. see next commit - some lb_ renames might be missing. feel free to provide patches. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
55 lines
1.3 KiB
C
55 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CPU_X86_MSR_H
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#define CPU_X86_MSR_H
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/* standard MSR operations, everyone has written these one hundred times */
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struct msr {
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u32 lo;
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u32 hi;
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};
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struct msrinit {
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u32 msrnum;
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struct msr msr;
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};
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static inline struct msr rdmsr(u32 index)
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{
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struct msr result;
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__asm__ __volatile__ (
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"rdmsr"
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: "=a" (result.lo), "=d" (result.hi)
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: "c" (index)
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);
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return result;
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}
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static inline void wrmsr(u32 index, struct msr msr)
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{
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__asm__ __volatile__ (
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"wrmsr"
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: /* No outputs */
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: "c" (index), "a" (msr.lo), "d" (msr.hi)
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);
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}
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#endif /* CPU_X86_MSR_H */
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