mirror of
https://github.com/fail0verflow/switch-coreboot.git
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Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1001 f3766cd6-281f-0410-b1cd-43a5c92072e9
191 lines
5.8 KiB
Text
191 lines
5.8 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/*
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chip northbridge/intel/i945
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device apic_cluster 0 on
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chip cpu/intel/socket_mFCPGA478
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device apic 0 on end
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end
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end
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device pci_domain 0 on
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device pci 00.0 on end # host bridge
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device pci 01.0 off end # i945 PCIe root port
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chip drivers/pci/onboard
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device pci 02.0 on end # vga controller
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register "rom_address" = "0xfff00000"
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end
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device pci 02.1 on end # display controller
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chip southbridge/intel/i82801gx
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register "ide_legacy_combined" = "0x1"
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register "ide_enable_primary" = "0x1"
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register "ide_enable_secondary" = "0x1"
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register "sata_ahci" = "0x0"
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe
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device pci 1c.1 on end # PCIe
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device pci 1c.2 on end # PCIe
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#device pci 1c.3 off end # PCIe port 4
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#device pci 1c.4 off end # PCIe port 5
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#device pci 1c.5 off end # PCIe port 6
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device pci 1d.0 on end # USB UHCI
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device pci 1d.1 on end # USB UHCI
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device pci 1d.2 on end # USB UHCI
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device pci 1d.3 on end # USB UHCI
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device pci 1d.7 on end # USB2 EHCI
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device pci 1e.0 on end # PCI bridge
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#device pci 1e.2 off end # AC'97 Audio
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#device pci 1e.3 off end # AC'97 Modem
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device pci 1f.0 on # LPC bridge
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chip superio/winbond/w83627thg
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device pnp 2e.0 off # Floppy
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end
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device pnp 2e.1 off # Parport
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end
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device pnp 2e.2 on
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on
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io 0x60 = 0x2f8
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irq 0x70 = 3
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irq 0xf1 = 4 # set IRMODE 0 # XXX not an irq
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end
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device pnp 2e.5 on # Keyboard+Mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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irq 0xf0 = 0x82 # HW accel A20.
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end
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device pnp 2e.7 on # GPIO1, GAME, MIDI
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io 0x62 = 0x330
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irq 0x70 = 9
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end
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device pnp 2e.8 on # GPIO2
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# all default
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end
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device pnp 2e.9 on # GPIO3/4
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irq 0x30 = 0x03 # does this work?
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irq 0xf0 = 0xfb # set inputs/outputs
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irq 0xf1 = 0x66
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end
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device pnp 2e.a off # ACPI
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end
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device pnp 2e.b on # HWM
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io 0x60 = 0xa00
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irq 0x70 = 0
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end
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end
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chip superio/winbond/w83627thg
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device pnp 4e.0 off # Floppy
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end
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device pnp 4e.1 off # Parport
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end
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device pnp 4e.2 on # COM3
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io 0x60 = 0x3e8
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irq 0x70 = 11
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end
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device pnp 4e.3 on # COM4
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io 0x60 = 0x2e8
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irq 0x70 = 10
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end
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device pnp 4e.5 off # Keyboard
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end
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device pnp 4e.7 off # GPIO1, GAME, MIDI
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end
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device pnp 4e.8 off # GPIO2
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end
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device pnp 4e.9 off # GPIO3/4
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end
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device pnp 4e.a off # ACPI
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end
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device pnp 4e.b off # HWM
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end
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end
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end
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#device pci 1f.1 off end # IDE
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device pci 1f.2 on end # SATA
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device pci 1f.3 on end # SMBus
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#device pci 1f.4 off end # Realtek ID Codec
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end
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end
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end
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*/
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/{
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device_operations="dbm690t";
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mainboard_vendor = "AMD";
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mainboard_name = "Serengeti";
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cpus { };
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apic@0 {
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};
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domain@0 {
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/config/("northbridge/amd/k8/domain");
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pci@1,0{
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};
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/* guesses; we need a real lspci */
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pci0@18,0 {
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/config/("northbridge/amd/k8/pci");
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/* make sure that the ht device is first, as it controls many other things. */
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pci0 {
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/config/("southbridge/amd/rs690/ht.dts");
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};
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pci1{
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/config/("southbridge/amd/rs690/gfx.dts");
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};
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pci2{
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/config/("southbridge/amd/rs690/pcie.dts");
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};
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pci4{
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/config/("southbridge/amd/sb600/hda.dts");
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};
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pci5{
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/config/("southbridge/amd/sb600/usb.dts");
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};
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pci6{
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/config/("southbridge/amd/sb600/usb2.dts");
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};
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};
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pci1@18,0 {
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/config/("northbridge/amd/k8/pci");
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};
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pci2@18,0 {
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/config/("northbridge/amd/k8/pci");
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/* just for illustrating link #2 */
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pci@2,0{
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};
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};
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pci@18,1 {};
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pci@18,2 {};
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pci@18,3 {};
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ioport@2e {
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/config/("superio/ite/it8712f/dts");
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com1enable = "1";
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};
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};
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};
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