Ronald G. Minnich e0031f798f I am well aware this does not compile :-) ... But we can start to build it now. Add the serengeti. Now comes the fun part: trying to get it to build. Be aware that things have changed. Stage1 is going to need to start up the APs, load the microcode, before we can event attempt to run initram. So we're going to need more sophisticated code than we've had in the past. Note also that copying cache_as_ram_auto.c and hacking it is NOT an option. We're going to have to recreate stage 1 and initram from scratch. I expect this to improve the code anyway. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com Acked-by: Ronald G. Minnich <rminnich@gmail.com git-svn-id: svn://coreboot.org/repository/coreboot-v3@773 f3766cd6-281f-0410-b1cd-43a5c92072e9		2008-08-15 22:04:31 +00:00
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amd	I am well aware this does not compile :-)	2008-08-15 22:04:31 +00:00
intel/i82371eb	Minor cosmetic and/or license header fixes (trivial).	2008-08-11 21:01:54 +00:00
nvidia/mcp55	First cut at sanity in the northbridge. Break out functions so that there is some meaning to what is in what.	2008-08-14 16:31:24 +00:00