mirror of
https://github.com/fail0verflow/switch-coreboot.git
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e0031f798f
But we can start to build it now. Add the serengeti. Now comes the fun part: trying to get it to build. Be aware that things have changed. Stage1 is going to need to start up the APs, load the microcode, before we can event attempt to run initram. So we're going to need more sophisticated code than we've had in the past. Note also that copying cache_as_ram_auto.c and hacking it is NOT an option. We're going to have to recreate stage 1 and initram from scratch. I expect this to improve the code anyway. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com Acked-by: Ronald G. Minnich <rminnich@gmail.com git-svn-id: svn://coreboot.org/repository/coreboot-v3@773 f3766cd6-281f-0410-b1cd-43a5c92072e9
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define _MAINOBJECT
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <cpu.h>
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#include <amd/k8/k8.h>
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#include <southbridge/nvidia/mcp55/mcp55_smbus.h>
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#include <mc146818rtc.h>
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#include <spd.h>
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# warning fix hard_reset
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void hard_reset(void)
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{
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}
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void memreset_setup(void)
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{
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}
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void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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/**
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* main for initram for the Gigabyte m57sli.
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*/
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int main(void)
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{
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printk(BIOS_DEBUG, "Hi there from stage1\n");
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post_code(POST_START_OF_MAIN);
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printk(BIOS_DEBUG, "stage1 returns\n");
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return 0;
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}
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