mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
dff619441a
The ICH7 SPIBAR offset and registers are different from later generation. ICH8 has a different offset from later generation. ICH6 has no SPI controller. BUG=None BRANCH=None TEST=None Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I7691bce619089b15805114047bcb1fd121a5722b Reviewed-on: https://chromium-review.googlesource.com/425276 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> |
||
|---|---|---|
| .. | ||
| ahci.c | ||
| amb.c | ||
| cpu.c | ||
| gfx.c | ||
| gpio.c | ||
| inteltool.8 | ||
| inteltool.c | ||
| inteltool.h | ||
| ivy_memory.c | ||
| Makefile | ||
| memory.c | ||
| pcie.c | ||
| powermgt.c | ||
| rootcmplx.c | ||
| spi.c | ||