switch-coreboot/src
Kyösti Mälkki df6eb79a22 intel/x4x: Do not use scratchpad register for ACPI S3
If S3 support was implemented for this platform later on, use
romstage handoff structure instead.

Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
2016-07-15 16:57:57 +02:00
..
acpi arch/x86: provide common Intel ACPI hardware definitions 2016-07-15 08:31:21 +02:00
arch arch/x86: provide common Intel ACPI hardware definitions 2016-07-15 08:31:21 +02:00
commonlib region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu AMD binaryPI: Use common romstage ram stack 2016-07-15 12:31:07 +02:00
device device: i2c: Add support for I2C bus operations 2016-06-09 17:05:40 +02:00
drivers drivers/intel/fsp1_1: align on using ACPI_Sx definitions 2016-07-15 08:31:09 +02:00
ec ec/google/chromeec: provide common SMI handler helpers 2016-07-15 08:35:29 +02:00
include lib: add poweroff() declaration 2016-07-15 08:35:15 +02:00
lib AGESA: Use common romstage ram stack 2016-07-15 12:18:54 +02:00
mainboard mainboards/skylake: use common Chrome EC SMI helpers 2016-07-15 08:36:24 +02:00
northbridge intel/x4x: Do not use scratchpad register for ACPI S3 2016-07-15 16:57:57 +02:00
soc soc/intel/skylake: provide poweroff() implementation 2016-07-15 08:36:12 +02:00
southbridge southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions 2016-07-15 08:34:46 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections 2016-07-15 00:40:19 +02:00
Kconfig Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-10 04:03:31 +02:00