mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
- Rename chip_config chip_operations throughout the tree - Fix Config.lb on most of the Opteron Ports - Fix the amd 8000 chipset support for setting the subsystem vendor and device ids - Add detection of devices that are on the motherboard (i.e. In Config.lb) - Baby step in getting the resource limit handling correct, Ignore fixed resources - Only call enable_childrens_resources on devices we know will have children For some busses like i2c it is non-sense and we don't want it. - Set the resource limits for pnp devices resources. - Improve the resource size detection for pnp devices. - Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels - Added a header file to hold the prototype of isa_dma_init - Fixed most of the superio chips so the should work now, the via superio pci device is the exception. - The code compiles and runs so it is time for me to go to bed. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
173 lines
5 KiB
C
173 lines
5 KiB
C
#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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/**
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* Read the resources for the root device,
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* that encompass the resources for the entire system.
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* @param root Pointer to the device structure for the system root device
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*/
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void root_dev_read_resources(device_t root)
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{
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struct resource *resource;
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/* Initialize the system wide io space constraints */
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resource = new_resource(root, 0);
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resource->base = 0x400;
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resource->size = 0;
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resource->align = 0;
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resource->gran = 0;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO;
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compute_allocate_resource(&root->link[0], resource,
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IORESOURCE_IO, IORESOURCE_IO);
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(root, 1);
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resource->base = 0;
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resource->size = 0;
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resource->align = 0;
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resource->gran = 0;
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resource->limit = 0xffffffffUL;
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resource->flags = IORESOURCE_MEM;
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compute_allocate_resource(&root->link[0], resource,
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IORESOURCE_MEM, IORESOURCE_MEM);
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}
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/**
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* Write the resources for the root device,
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* and every device under it which are all of the devices.
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* @param root Pointer to the device structure for the system root device
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*/
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void root_dev_set_resources(device_t root)
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{
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struct bus *bus;
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bus = &root->link[0];
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compute_allocate_resource(bus,
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&root->resource[0], IORESOURCE_IO, IORESOURCE_IO);
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compute_allocate_resource(bus,
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&root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
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assign_resources(bus);
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}
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/**
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* @brief Scan devices on static buses.
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*
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* The enumeration of certain buses is purely static. The existence of
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* devices on those buses can be completely determined at compile time
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* by the config file. Typical expamles are the 'PNP' devices on a legacy
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* ISA/LPC bus. There is no need of probing of any kind, the only thing
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* we have to do is to walk through the bus and enable or disable devices
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* as indicated in the config file.
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*
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* This function is the default scan_bus() method for LPC bridges.
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*
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* @param root Pointer to the device structure for the system root device
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* @param max Maximum bus number allowed in the system.
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* @return Largest bus number used.
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*/
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unsigned int scan_static_bus(device_t bus, unsigned int max)
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{
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device_t child;
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unsigned link;
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printk_debug("%s for %s\n", __func__, dev_path(bus));
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for(link = 0; link < bus->links; link++) {
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for(child = bus->link[link].children; child; child = child->sibling) {
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if (child->chip_ops && child->chip_ops->enable_dev) {
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child->chip_ops->enable_dev(child);
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}
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if (child->ops && child->ops->enable) {
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child->ops->enable(child);
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}
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printk_debug("%s %s\n",
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dev_path(child),
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child->enabled?"enabled": "disabled");
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}
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}
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for(link = 0; link < bus->links; link++) {
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for(child = bus->link[link].children; child; child = child->sibling) {
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if (!child->ops || !child->ops->scan_bus)
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continue;
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printk_debug("%s scanning...\n", dev_path(child));
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max = child->ops->scan_bus(child, max);
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}
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}
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printk_debug("%s done\n", __func__);
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return max;
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}
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/**
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* @brief Enable resources for children devices
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*
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* @param dev the device whos children's resources are to be enabled
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*
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* This function is call by the enable_resource() indirectly via the
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* enable_resources() method of devices.
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*
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* Indirect mutual recursion:
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*/
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void enable_childrens_resources(device_t dev)
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{
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unsigned link;
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for(link = 0; link < dev->links; link++) {
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device_t child;
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for(child = dev->link[link].children; child; child = child->sibling) {
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enable_resources(child);
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}
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}
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}
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void root_dev_enable_resources(device_t dev)
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{
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enable_childrens_resources(dev);
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}
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/**
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* @brief Scan root bus for generic systems
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*
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* @param root The root device structure
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* @param max The current bus number scanned so fat, usually 0x00
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*
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* This function is the default scan_bus() method of the dynamic root device.
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* The bus heirachy is rooted at the host/northbridge. The northbridge of a
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* generic PCI bus system is at Bus 0, Dev 0, Fun 0 so we scan the whole PCI
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* buses from there.
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*/
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unsigned int root_dev_scan_bus(device_t root, unsigned int max)
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{
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return scan_static_bus(root, max);
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}
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void root_dev_init(device_t root)
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{
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}
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/**
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* @brief Default device operation for root device
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*
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* This is the default device operation for root devices in PCI based systems.
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* These operations should be fully usable as is. However the
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* chip_operations::dev_enable of a motherboard can override this if you
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* want non-default behavior. Currently src/mainboard/arima/hdama/mainbaord.c
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* does this for debugging purposes.
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*/
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struct device_operations default_dev_ops_root = {
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.read_resources = root_dev_read_resources,
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.set_resources = root_dev_set_resources,
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.enable_resources = root_dev_enable_resources,
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.init = root_dev_init,
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.scan_bus = root_dev_scan_bus,
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};
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/**
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* @brief The root of dynamic device tree.
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*
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* This is the root of the dynamic device tree. A PCI tree always has
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* one bus, bus 0. Bus 0 contains devices and bridges.
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*/
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extern struct device dev_root;
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