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https://github.com/fail0verflow/switch-coreboot.git
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da9286b479
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@722 f3766cd6-281f-0410-b1cd-43a5c92072e9
121 lines
4.3 KiB
C
121 lines
4.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 Ronald G. Minnich
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/**
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* setup a resource map.
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* for PCRM entries, add a pci device offset, and a pci "OR value offset"
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* for IO8 and IO32 entries, add an io base offset.
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* This function combines a bunch of seperate functions that were scattered
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* throughout v2. It may be awkward but it does allow for one rmap for
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* all settings, which is handy. See include/arch/x86/cpu.h for usage on
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* how to set up a resource map.
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*
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* @param rm The resource map
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* @param max The map size
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* @param offset_bdf pci device offset. Note this is a u32 in
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* busdevfn format. See PCI_BDF macro if you are not sure what that is.
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* @param offset_pciio added to the OR value for setting up PCI IO
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* @param offset_io offset from the io base in the resource map
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*/
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/* NOTE: By doing the config write in this manner we guarantee that this
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* will work in stage1 or stage2.
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*/
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#define pci_read_config32(bus, dev, where) pci_cf8_conf1.read32(NULL, r->pcm.bus, dev, where)
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#define pci_write_config32(bus, dev, where, what) pci_cf8_conf1.write32(NULL, r->pcm.bus, dev, where, what)
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void setup_resource_map_x_offset(const rmap *rm, u32 max,
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u32 offset_bdf, u32 offset_pciio,
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u32 offset_io)
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{
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u32 i;
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printk(BIOS_DEBUG, "setting up resource map ex offset....\n");
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for(i = 0; i < max; i++, rm++) {
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switch (rm->type){
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case TPCIRM:
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{
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u32 dev;
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unsigned where;
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unsigned long reg;
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u8 offset_devfn = offset_bdf;
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#warning make sure offset_bus is right for extended PCI addressing
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u32 offset_bus = offset_bdf >> 8;
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printk(BIOS_DEBUG, "(%x+%x,%x+%x,%x+%x,%x) & %08x | %08x+%08x\n", rm->pcm.bus,
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offset_bus, rm->pcm.dev+offset_devfn>>3,
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rm->pcm.fn, offset_devfn&3, rm->pcm.reg,
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rm->pcm.and,rm->pcm.or, offset_pciio);
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dev = rm->pcm.dev;
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where = rm->pcm.reg;
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dev <<= 3;
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dev |= rm->pcm.fn;
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dev += offset_devfn;
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reg = pci_read_config32(rm->pcm.bus + offset_bus, dev, where);
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reg &= rm->pcm.and;
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reg |= rm->pcm.or + offset_pciio;
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pci_write_config32(rm->pcm.bus, dev, where, reg);
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}
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break;
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case TIO8:
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{
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u32 where;
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u8 reg;
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printk(BIOS_DEBUG, "(%04x+%04x) & %02x | %02xx\n", rm->port, offset_io, rm->pcm.and,rm->pcm.or);
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where = rm->port + offset_io;
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reg = inb(where);
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reg &= rm->and;
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reg |= rm->or;
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outb(reg, where);
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}
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break;
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case TIO32:
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{
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u32 where;
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u32 reg;
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printk(BIOS_DEBUG, "(%04x+%04x) & %02x | %02xx\n", rm->port, offset_io, rm->pcm.and,rm->pcm.or);
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where = rm->port + offset_io;
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reg = inl(where);
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reg &= rm->and;
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reg |= rm->or;
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outl(reg, where);
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}
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break;
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} // switch
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}
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printk(BIOS_DEBUG, "done.\n");
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}
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/**
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* setup a resource map
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* @param rm The resource map
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* @param max The map size
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*/
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void setup_resource_map(const struct rmap *rm, u32 max)
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{
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setup_resource_map_x_offset(rm, max);
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}
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