mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
da6d92ba11
As I mentioned a few weeks ago, I am in the process of porting this board: http://www.technexion.com/products/embedded_boards/tim-8690-mt.html This board has a dual BIOS , choosable with a jumper - much like the BIOS savier from before - so it is a pleasure to work with as a linuxbios developer. It is still a work in progress, however , I already submit the patch. All on board devices and slots work as expected, only need some more stress testing with the RAM, acpi, etc.. Signed-off-by: Daniel Toussaint <daniel@dmhome.net> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
149 lines
3 KiB
Text
149 lines
3 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* simple name description */
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/*
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Scope (_SB) {
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Device(PCI0) {
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Device(SATA) {
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Name(_ADR, 0x00120000)
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Include ("sata.asl")
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}
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}
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}
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*/
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Name(STTM, Buffer(20) {
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0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
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0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00,
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0x1f, 0x00, 0x00, 0x00
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})
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/* Start by clearing the PhyRdyChg bits */
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Method(_INI) {
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\_GPE._L1F()
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}
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Device(PMRY)
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{
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Name(_ADR, 0)
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Method(_GTM, 0x0, NotSerialized) {
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Return(STTM)
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}
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Method(_STM, 0x3, NotSerialized) {}
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Device(PMST) {
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Name(_ADR, 0)
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Method(_STA,0) {
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if (LGreater(P0IS,0)) {
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return (0x0F) /* sata is visible */
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}
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else {
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return (0x00) /* sata is missing */
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}
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}
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}/* end of PMST */
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Device(PSLA)
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{
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Name(_ADR, 1)
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Method(_STA,0) {
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if (LGreater(P1IS,0)) {
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return (0x0F) /* sata is visible */
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}
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else {
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return (0x00) /* sata is missing */
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}
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}
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} /* end of PSLA */
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} /* end of PMRY */
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Device(SEDY)
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{
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Name(_ADR, 1) /* IDE Scondary Channel */
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Method(_GTM, 0x0, NotSerialized) {
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Return(STTM)
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}
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Method(_STM, 0x3, NotSerialized) {}
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Device(SMST)
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{
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Name(_ADR, 0)
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Method(_STA,0) {
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if (LGreater(P2IS,0)) {
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return (0x0F) /* sata is visible */
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}
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else {
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return (0x00) /* sata is missing */
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}
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}
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} /* end of SMST */
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Device(SSLA)
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{
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Name(_ADR, 1)
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Method(_STA,0) {
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if (LGreater(P3IS,0)) {
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return (0x0F) /* sata is visible */
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}
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else {
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return (0x00) /* sata is missing */
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}
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}
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} /* end of SSLA */
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} /* end of SEDY */
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/* SATA Hot Plug Support */
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Scope(\_GPE) {
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Method(_L1F,0x0,NotSerialized) {
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if (\_SB.P0PR) {
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if (LGreater(\_SB.P0IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P0PR)
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}
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if (\_SB.P1PR) {
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if (LGreater(\_SB.P1IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P1PR)
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}
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if (\_SB.P2PR) {
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if (LGreater(\_SB.P2IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P2PR)
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}
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if (\_SB.P3PR) {
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if (LGreater(\_SB.P3IS,0)) {
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sleep(32)
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}
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Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */
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store(one, \_SB.P3PR)
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}
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}
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}
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