switch-coreboot/src
Duncan Laurie d9af3cecae device: Add an ACPI device name and path concept to devices
Add a function to "struct device_operations" to return the ACPI name
for the device, and helper functions to find this name (either from
the device or its parent) and to build a fully qualified ACPI path
from the root device.

This addition will allow device drivers to generate their ACPI AML in
the SSDT at boot, with customization supplied by devicetree.cb,
instead of needing custom DSDT ASL for every mainboard.

The root device acpi_name is defined as "\\_SB" and is used to start
the path when building a fully qualified name.

This requires SOC support to provide handlers for returning the ACPI
name for devices that it owns, and those names must match the objects
declared in the DSDT.  The handler can be done either in each device
driver or with a global handler for the entire SOC.

Simplified example of how this can be used for an i2c device declared
in devicetree.cb with:

  chip soc/intel/skylake          # "\_SB" (from root device)
    device domain 0 on            # "PCI0"
      device pci 19.2 on          # "I2C4"
        chip drivers/i2c/test0
          device i2c 1a.0 on end  # "TST0"
        end
      end
    end
  end

And basic SSDT generating code in the device driver:

  acpigen_write_scope(acpi_device_scope(dev));
  acpigen_write_device(acpi_device_name(dev));
  acpigen_write_string("_HID", "TEST0000");
  acpigen_write_byte("_UID", 0);
  acpigen_pop_len(); /* device */
  acpigen_pop_len(); /* scope */

Will produce this ACPI code:

  Scope (\_SB.PCI0.I2C4) {
    Device (TST0) {
      Name (_HID, "TEST0000")
      Name (_UID, 0)
    }
  }

Change-Id: Ie149595aeab96266fa5f006e7934339f0119ac54
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14840
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-21 05:59:52 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch device: Add an ACPI device name and path concept to devices 2016-05-21 05:59:52 +02:00
commonlib cbfstool/fsp: Rename fsp1_1_relocate 2016-05-11 18:38:28 +02:00
console arch/x86: introduce postcar stage/phase 2016-03-23 14:24:30 +01:00
cpu AGESA vendorcode: Build a common amdlib 2016-05-18 10:44:43 +02:00
device device: Add an ACPI device name and path concept to devices 2016-05-21 05:59:52 +02:00
drivers drivers/intel/fsp2_0: Add recipes for FSP blobs in CBFS 2016-05-18 07:04:10 +02:00
ec ec/google/chromeec/acpi: Add MKBP support 2016-05-18 20:22:38 +02:00
include device: Add an ACPI device name and path concept to devices 2016-05-21 05:59:52 +02:00
lib hexstrtobin: Add a library function to decode ASCII hex into binary 2016-05-21 05:58:51 +02:00
mainboard rockchip: rk3399: enable sdhci clk for emmc 2016-05-18 20:23:42 +02:00
northbridge intel/sch: Merge northbridge and southbridge in src/soc 2016-05-17 21:38:17 +02:00
soc soc/intel/apollolake: Relocate FSP-M during insertion in CBFS 2016-05-19 18:45:16 +02:00
southbridge AGESA vendorcode: Build a common amdlib 2016-05-18 10:44:43 +02:00
superio sio/winbond: Expose enter/exit configuration state functions 2016-05-20 04:11:58 +02:00
vendorcode AGESA vendorcode: Build a common amdlib 2016-05-18 10:44:43 +02:00
Kconfig src/Kconfig: Move acpi Kconfig below chipset Kconfigs 2016-05-19 19:29:59 +02:00