mirror of
https://github.com/fail0verflow/switch-coreboot.git
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d8e532cbfe
BUG=none
BRANCH=none
TEST=none
Change-Id: Id20a4c5f8c0f52dc19a52d0220f9b3092b7d491f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 70a8e34853
Original-Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/18704
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/458637
24 lines
853 B
C
24 lines
853 B
C
#include <arch/io.h>
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/* Just re-define this instead of including i945.h. It blows up romcc. */
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#define PCIEXBAR 0x48
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static void bootblock_northbridge_init(void)
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{
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uint32_t reg;
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/*
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* The "io" variant of the config access is explicitly used to
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* setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT is set to
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* to true. That way all subsequent non-explicit config accesses use
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* MCFG. This code also assumes that bootblock_northbridge_init() is
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* the first thing called in the non-asm boot block code. The final
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* assumption is that no assembly code is using the
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* CONFIG_MMCONF_SUPPORT option to do PCI config acceses.
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*
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* The PCIEXBAR is assumed to live in the memory mapped IO space under
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* 4GiB.
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*/
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reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
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pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg);
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}
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