switch-coreboot/device/pci_ops.c
Ronald G. Minnich 28ecbeab88 The K8 is one example, but there are other devices (e.g. I2C) that also have
multiple links. The way this was done in v2 was a big confusing; this way is 
less so. 

The changes are easy. Getting them right has been hard :-)

First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0

We have to have the same pcidevfn on these because that is how the k8 works. 
But the unit numbers (pci0, pci1, etc.) distinguish them. 

The dts will properly generate a "v3 device code" 
compatible static tree that puts the links in the right place in the 
data structure. 

The changes to dts are trivial. 
As before, dts nodes with children are understood to be a bridge. 
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};


This entry has no children in the dts. 
How does dt compiler know it is a bridge? It can not know unless 
we add information to the dts for that northbridge part. 
To ensure that all bridge devices are detected, we support the following: 
if a dts node for a device has a bridge property, e.g.: 
 {
        device_operations = "k8_ops";
       bridge;
 };

The dt compiler will treat it as a bridge whether it has children or not. 

Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty, 
or what might be in the socket. 

This code has been tested on dbe62 and k8 simnow, and works on each. 
It is minimal in size and it does what we need. I hope it resolves our 
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!

Also included in this patch are new debug prints in k8 north. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-09-17 16:36:20 +00:00

101 lines
3 KiB
C

/*
* This file is part of the coreboot project.
*
* Copyright (C) 2004 Linux Networx
* (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console.h>
#include <device/device.h>
#include <pciconf.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <types.h>
/**
* Walk up the tree from the current dev, in an attempt to find a
* bus that has ops_pci_bus set. The assumption here being that if it
* has ops_pci_bus set, then it can do bus operations.
*/
static struct bus *get_pbus(struct device *dev)
{
struct bus *pbus = dev->bus;
while (pbus && pbus->dev && !ops_pci_bus(pbus)) {
if (pbus->dev == dev) {
printk(BIOS_EMERG, "Loop: dev->dtsname dev->bus->dev\n");
printk(BIOS_EMERG, "To fix this, set ops_pci_bus in dts\n");
die("loop due to insufficient dts");
}
pbus = pbus->dev->bus;
}
if (!pbus || !pbus->dev || !pbus->dev->ops
|| !pbus->dev->ops->ops_pci_bus) {
printk(BIOS_ALERT, "%s: %s(%s) Cannot find PCI bus operations",
__func__, dev->dtsname, dev_path(dev));
die("");
}
return pbus;
}
u8 pci_read_config8(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read8(PCI_BDEVFN(dev->bus->secondary,
dev->path.pci.devfn),
where);
}
u16 pci_read_config16(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read16(PCI_BDEVFN(dev->bus->secondary,
dev->path.pci.devfn),
where);
}
u32 pci_read_config32(struct device *dev, unsigned int where)
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read32(PCI_BDEVFN(dev->bus->secondary,
dev->path.pci.devfn),
where);
}
void pci_write_config8(struct device *dev, unsigned int where, u8 val)
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write8(PCI_BDEVFN(dev->bus->secondary,
dev->path.pci.devfn),
where, val);
}
void pci_write_config16(struct device *dev, unsigned int where, u16 val)
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write16(PCI_BDEVFN(dev->bus->secondary,
dev->path.pci.devfn),
where, val);
}
void pci_write_config32(struct device *dev, unsigned int where, u32 val)
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write32(PCI_BDEVFN(dev->bus->secondary,
dev->path.pci.devfn),
where, val);
}