mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d7e12d6d07
This is from v2. Once again, the pattern: - save the chip name for the common enable parts, hence i82801gx.c - remove the leading i82801_ from most other bits, since we compile in different directories now - Every device of a type has a distinct .c file (e.g. pcie.c) - Each device of a type may be realized in more than one bit of silicon, and have more than one set of operations, although code is common. These are placed into distinct operations structs (see pcie.c) - for every distinct device, there is a .dts file. This set of rules makes for simple cross-part standardization of code. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@991 f3766cd6-281f-0410-b1cd-43a5c92072e9
122 lines
3.4 KiB
C
122 lines
3.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
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#define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
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#include "chip.h"
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extern void i82801gx_enable(device_t dev);
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#define PCI_DMA_CFG 0x90
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#define SERIRQ_CNTL 0x64
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#define GEN_CNTL 0xd0
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#define GEN_STS 0xd4
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#define RTC_CONF 0xd8
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#define GEN_PMCON_1 0xa0
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#define GEN_PMCON_2 0xa2
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#define GEN_PMCON_3 0xa4
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#define PMBASE 0x40
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#define ACPI_CNTL 0x44
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#define BIOS_CNTL 0x4E
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#define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
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#define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
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#define PIRQA_ROUT 0x60
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#define PIRQB_ROUT 0x61
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#define PIRQC_ROUT 0x62
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#define PIRQD_ROUT 0x63
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#define PIRQE_ROUT 0x68
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#define PIRQF_ROUT 0x69
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#define PIRQG_ROUT 0x6A
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#define PIRQH_ROUT 0x6B
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#define FUNC_DIS 0xF2
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define SBUS_NUM 0x19
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#define SUB_BUS_NUM 0x1A
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#define SMLT 0x1B
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#define IOBASE 0x1C
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#define IOLIM 0x1D
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#define MEMBASE 0x20
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#define MEMLIM 0x22
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#define CNF 0x50
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#define MTT 0x70
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#define PCI_MAST_STS 0x82
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/* GEN_PMCON_3 bits */
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#define RTC_BATTERY_DEAD (1 << 2)
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#define RTC_POWER_FAILED (1 << 1)
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#define SLEEP_AFTER_POWER_FAIL (1 << 0)
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/* PCI Configuration Space (D31:F1) */
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#define INTR_LN 0x3c
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#define IDE_TIM_PRI 0x40 /* IDE timings, primary */
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#define IDE_DECODE_ENABLE (1 << 15)
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#define IDE_SITRE (1 << 14)
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#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
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#define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */
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#define SIG_MODE_NORMAL (0 << 16)
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#define SIG_MODE_TRISTATE (1 << 16)
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#define SIG_MODE_DRIVELOW (2 << 16)
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#define FAST_PCB1 (1 << 13)
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#define FAST_PCB0 (1 << 12)
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#define PCB1 (1 << 1)
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#define PCB0 (1 << 0)
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/* PCI Configuration Space (D31:F3) */
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#define SMB_BASE 0x20
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#define HOSTC 0x40
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/* HOSTC bits */
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#define I2C_EN (1 << 2)
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#define SMB_SMI_EN (1 << 1)
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#define HST_EN (1 << 0)
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/* SMBus I/O bits.
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* TODO: It does not matter where we put the SMBus IO base, as long as we keep
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* consistent and don't interfere with other devices. Stage2 will relocate
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* this anyways. But it's a general problem we have not solved in the brightest
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* possible way.
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*/
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/* #define SMBUS_IO_BASE 0x1000 */
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#define SMBUS_IO_BASE 0x0400
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#define SMBHSTSTAT 0x0
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#define SMBHSTCTL 0x2
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#define SMBHSTCMD 0x3
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#define SMBXMITADD 0x4
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#define SMBHSTDAT0 0x5
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#define SMBHSTDAT1 0x6
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#define SMBBLKDAT 0x7
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#define SMBTRNSADD 0x9
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#define SMBSLVDATA 0xa
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#define SMLINK_PIN_CTL 0xe
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#define SMBUS_PIN_CTL 0xf
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#define SMBUS_TIMEOUT (10 * 1000 * 100)
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/* HPET, if present */
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#define HPET_ADDR 0xfed0000
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#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */
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