mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d65509de14
with the respective board. Of course, the user can still override the size in menuconfig. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
54 lines
1 KiB
Text
54 lines
1 KiB
Text
config BOARD_INTEL_XE7501DEVKIT
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bool "XE7501devkit"
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select ARCH_X86
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select CPU_INTEL_SOCKET_MPGA604
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select NORTHBRIDGE_INTEL_E7501
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select SOUTHBRIDGE_INTEL_I82870
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select SOUTHBRIDGE_INTEL_I82801CA
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select SUPERIO_SMSC_LPC47B272
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select HAVE_PIRQ_TABLE
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select HAVE_MP_TABLE
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select UDELAY_TSC
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_TABLES
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select BOARD_ROMSIZE_KB_2048
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config MAINBOARD_DIR
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string
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default intel/xe7501devkit
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depends on BOARD_INTEL_XE7501DEVKIT
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config LB_CKS_RANGE_START
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int
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default 128
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depends on BOARD_INTEL_XE7501DEVKIT
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config LB_CKS_RANGE_END
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int
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default 130
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depends on BOARD_INTEL_XE7501DEVKIT
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config LB_CKS_LOC
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int
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default 131
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depends on BOARD_INTEL_XE7501DEVKIT
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config MAINBOARD_PART_NUMBER
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string
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default "EIDXE7501DEVKIT"
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depends on BOARD_INTEL_XE7501DEVKIT
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config IRQ_SLOT_COUNT
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int
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default 12
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depends on BOARD_INTEL_XE7501DEVKIT
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config MAX_CPUS
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int
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default 2
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depends on BOARD_INTEL_XE7501DEVKIT
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config MAX_PHYSICAL_CPUS
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int
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default 2
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depends on BOARD_INTEL_XE7501DEVKIT
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