mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d4480beaec
This patch makes specific devices use the updated resource allocation code.
The changes necessary are:
1. Remove all calls to compute_allocate_resources.
2. Don't store resources except in phase4_set_resources.
northbridge/amd/k8/pci.c:
Remove calls to compute_allocate_resource.
Change phase4_assign_resources to phase4_set_resources
southbridge/amd/amd8132/amd8132_bridge.c:
Remove NPUML and NPUMB.
Add a warning for bus disabling.
Remove bridge_{read|set}_resources (they were there for NPUML)
southbridge/nvidia/mcp55/lpc.c:
southbridge/amd/sb600/lpc.c:
Remove references to have_resources.
southbridge/amd/amd8111/lpc.c:
Add resources for subtractive IO and ROM.
northbridge/amd/k8/domain.c:
northbridge/intel/i440bxemulation/i440bx.c:
northbridge/amd/geodelx/geodelx.c:
northbridge/intel/i945/northbridge.c:
northbridge/via/cn700/stage2.c:
Change phase4_assign_resources->phase4_set_resources.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@1090 f3766cd6-281f-0410-b1cd-43a5c92072e9
99 lines
3.7 KiB
C
99 lines
3.7 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright (C) 2000 Ron Minnich, Advanced Computing Lab, LANL
|
|
* Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
|
|
* Copyright (C) 2008 Patrick Georgi <patrick@georgi-clan.de>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
|
|
/*
|
|
* This software and ancillary information (herein called SOFTWARE )
|
|
* called LinuxBIOS is made available under the terms described
|
|
* here. The SOFTWARE has been approved for release with associated
|
|
* LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
|
|
* been authored by an employee or employees of the University of
|
|
* California, operator of the Los Alamos National Laboratory under
|
|
* Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
|
|
* U.S. Government has rights to use, reproduce, and distribute this
|
|
* SOFTWARE. The public may copy, distribute, prepare derivative works
|
|
* and publicly display this SOFTWARE without charge, provided that this
|
|
* Notice and any statement of authorship are reproduced on all copies.
|
|
* Neither the Government nor the University makes any warranty, express
|
|
* or implied, or assumes any liability or responsibility for the use of
|
|
* this SOFTWARE. If SOFTWARE is modified to produce derivative works,
|
|
* such modified SOFTWARE should be clearly marked, so as not to confuse
|
|
* it with the version available from LANL.
|
|
*/
|
|
|
|
#include <types.h>
|
|
#include <console.h>
|
|
#include <device/device.h>
|
|
#include <device/pci.h>
|
|
#include <string.h>
|
|
#include <io.h>
|
|
#include "i440bx.h"
|
|
#include <statictree.h>
|
|
|
|
/* Here are the ops for 440BX as a PCI domain. */
|
|
|
|
static int inb_cmos(int port)
|
|
{
|
|
outb(port, 0x70);
|
|
return inb(0x71);
|
|
}
|
|
|
|
static void pci_domain_set_resources(struct device *dev)
|
|
{
|
|
struct device *mc_dev;
|
|
u32 tolmk; /* Top of low mem, Kbytes. */
|
|
int idx;
|
|
/* read large mem memory descriptor
|
|
for <16 MB read the more detailed small mem descriptor
|
|
all values in kbytes */
|
|
tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64;
|
|
if (tolmk <= 16 * 1024) {
|
|
tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30);
|
|
}
|
|
printk(BIOS_WARNING, "Ignoring chipset specified RAM size. Using dts "
|
|
"settings of %d kB instead.\n", tolmk);
|
|
mc_dev = dev->link[0].children;
|
|
if (mc_dev) {
|
|
idx = 10;
|
|
/* 0 .. 640 kB */
|
|
ram_resource(dev, idx++, 0, 640);
|
|
/* Hole for VGA (0xA0000-0xAFFFF) graphics and text mode
|
|
* graphics (0xB8000-0xBFFFF) */
|
|
/* 768 kB .. Systop (in KB) */
|
|
ram_resource(dev, idx++, 768, tolmk - 768);
|
|
}
|
|
phase4_set_resources(&dev->link[0]);
|
|
}
|
|
|
|
/* Here are the operations for when the northbridge is running a PCI domain. */
|
|
/* See mainboard/emulation/qemu-x86 for an example of how these are used. */
|
|
struct device_operations i440bx_domain = {
|
|
.id = {.type = DEVICE_ID_PCI_DOMAIN,
|
|
{.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
|
|
.constructor = default_device_constructor,
|
|
.phase3_scan = pci_domain_scan_bus,
|
|
.phase4_read_resources = pci_domain_read_resources,
|
|
.phase4_set_resources = pci_domain_set_resources,
|
|
.phase5_enable_resources = enable_childrens_resources,
|
|
.phase6_init = 0,
|
|
.ops_pci_bus = &pci_cf8_conf1,
|
|
|
|
};
|