mirror of
https://github.com/fail0verflow/switch-coreboot.git
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d4088bcbbb
Factor out write_pirq_routing_table() for all GeodeLX targets. Compile tested on norwich, alix1c and dbe62. msm800sev is not affected and dbe61 is broken anyway. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> tested on alix1c. Boots, USB, graphics, and ethernet all work. Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://coreboot.org/repository/coreboot-v3@629 f3766cd6-281f-0410-b1cd-43a5c92072e9
77 lines
2.3 KiB
C
77 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <lib.h>
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#include <console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <msr.h>
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#include <io.h>
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#include <pirq_routing.h>
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#include <amd_geodelx.h>
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#include <irq_tables.h>
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#include "cs5536.h"
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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int i, j, k, num_entries;
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unsigned char pirq[4];
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u16 chipset_irq_map;
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u32 pciAddr, pirtable_end;
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struct irq_routing_table *pirq_tbl;
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pirtable_end = copy_pirq_routing_table(addr);
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/* Set up chipset IRQ steering. */
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pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C;
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chipset_irq_map = (PIRQD << 12 | PIRQC << 8 | PIRQB << 4 | PIRQA);
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printk(BIOS_DEBUG, "%s(%08X, %04X)\n", __FUNCTION__, pciAddr,
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chipset_irq_map);
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outl(pciAddr & ~3, 0xCF8);
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outl(chipset_irq_map, 0xCFC);
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pirq_tbl = (struct irq_routing_table *) (addr);
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num_entries = (pirq_tbl->size - 32) / 16;
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/* Set PCI IRQs. */
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for (i = 0; i < num_entries; i++) {
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printk(BIOS_DEBUG, "PIR Entry %d Dev/Fn: %X Slot: %d\n", i,
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pirq_tbl->slots[i].devfn, pirq_tbl->slots[i].slot);
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for (j = 0; j < 4; j++) {
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printk(BIOS_DEBUG, "INT: %c bitmap: %x ", 'A' + j,
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pirq_tbl->slots[i].irq[j].bitmap);
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/* Finds lsb in bitmap to IRQ#. */
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for (k = 0;
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(!((pirq_tbl->slots[i].irq[j].bitmap >> k) & 1))
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&& (pirq_tbl->slots[i].irq[j].bitmap != 0);
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k++);
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pirq[j] = k;
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printk(BIOS_DEBUG, "PIRQ: %d\n", k);
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}
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/* Bus, device, slots IRQs for {A,B,C,D}. */
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pci_assign_irqs(pirq_tbl->slots[i].bus,
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pirq_tbl->slots[i].devfn >> 3, pirq);
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}
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/* Put the PIR table in memory and checksum. */
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return pirtable_end;
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}
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