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https://github.com/fail0verflow/switch-coreboot.git
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6220b632e7
- I left LB_TAG_ intact because they are used by the payloads - file renames are still missing. see next commit - some lb_ renames might be missing. feel free to provide patches. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://coreboot.org/repository/coreboot-v3@564 f3766cd6-281f-0410-b1cd-43a5c92072e9
38 lines
1.3 KiB
C
38 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* It is based on the arch/i386/boot/setup.S file from the Linux kernel.
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*/
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/*
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! setup.S Copyright (C) 1991, 1992 Linus Torvalds
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!
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! some changes and additional features by Christoph Niemann,
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! March 1993/June 1994 (Christoph.Niemann@linux.org)
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*/
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#include <io.h>
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/*
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! well, that went ok, I hope. Now we have to reprogram the interrupts :-(
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! we put them right after the intel-reserved hardware interrupts, at
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! int 0x20-0x2F. There they won't mess up anything. Sadly IBM really
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! messed this up with the original PC, and they haven't been able to
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! rectify it afterwards. Thus the bios puts interrupts at 0x08-0x0f,
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! which is used for the internal hardware interrupts as well. We just
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! have to reprogram the 8259's, and it isn't fun.
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*/
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void setup_i8259(void)
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{
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outb(0x11, 0x20); /* Initialization sequence (8259A-1). */
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outb(0x11, 0xA0); /* Initialization sequence (8259A-2). */
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outb(0x20, 0x21); /* Start of hardware INTs (0x20). */
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outb(0x28, 0xA1); /* Start of hardware INTs 2 (0x28). */
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outb(0x04, 0x21); /* 8259-1 is master. */
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outb(0x02, 0xA1); /* 8259-2 is slave. */
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outb(0x01, 0x21); /* 8086 mode for both. */
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outb(0x01, 0xA1);
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outb(0xFF, 0xA1); /* Mask off all interrupts for now. */
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outb(0xFB, 0x21); /* Mask all IRQs but IRQ2 which is cascaded. */
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}
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