mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d17a8623a5
BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 Reviewed-on: http://review.coreboot.org/10740 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
/*
|
|
* This file is part of the coreboot project.
|
|
*
|
|
* Copyright 2014 Rockchip Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc.
|
|
*/
|
|
|
|
#include <arch/cache.h>
|
|
#include <arch/io.h>
|
|
#include <bootblock_common.h>
|
|
#include <console/console.h>
|
|
#include <soc/addressmap.h>
|
|
#include <soc/clock.h>
|
|
#include <soc/grf.h>
|
|
#include <soc/timer.h>
|
|
#include <symbols.h>
|
|
#include <timestamp.h>
|
|
|
|
void bootblock_soc_init(void)
|
|
{
|
|
timestamp_init(timestamp_get());
|
|
|
|
rkclk_init();
|
|
|
|
mmu_init();
|
|
/* Start with a clean slate. */
|
|
mmu_config_range(0, 4096, DCACHE_OFF);
|
|
/* SRAM is tightly wedged between registers, need to use subtables. Map
|
|
* write-through as equivalent for non-cacheable without XN on A17. */
|
|
mmu_config_range_kb((uintptr_t)_sram/KiB,
|
|
_sram_size/KiB, DCACHE_WRITETHROUGH);
|
|
dcache_mmu_enable();
|
|
|
|
rkclk_configure_crypto(148500*KHz);
|
|
}
|