mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
d08e69dd5e
The READ_CONF and WRITE_CONF functions would both do the wrong thing if the passed in BDF was not found. We should return and error to the caller, but not stop running the option ROM. Signed-off-by: Mark Marshall <mark.marshall@csr.com> I slightly reworked the patch: The 'CHECK' function seemed to be both wrong code and the wrong number. In fact the CHECK function was given the function number of the "Microsoft Real-Time Compression Interface". Since this is definitely wrong I removed the code. Dropped some unneeded scopes, too, to make the code easier to read. Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4910 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
240 lines
6 KiB
C
240 lines
6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2001 Ronald G. Minnich
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* Copyright (C) 2005 Nick.Barker9@btinternet.com
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <string.h>
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#ifdef CONFIG_COREBOOT_V2
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#include <console/console.h>
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#include <arch/io.h>
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#include <arch/registers.h>
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#define printk(x...) do_printk(x)
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#else
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#include <console.h>
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#include <io.h>
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#endif
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enum {
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PCIBIOS_CHECK = 0xb101,
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PCIBIOS_FINDDEV = 0xb102,
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PCIBIOS_READCONFBYTE = 0xb108,
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PCIBIOS_READCONFWORD = 0xb109,
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PCIBIOS_READCONFDWORD = 0xb10a,
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PCIBIOS_WRITECONFBYTE = 0xb10b,
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PCIBIOS_WRITECONFWORD = 0xb10c,
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PCIBIOS_WRITECONFDWORD = 0xb10d
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};
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// errors go in AH. Just set these up so that word assigns
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// will work. KISS.
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enum {
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PCIBIOS_SUCCESSFUL = 0x0000,
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PCIBIOS_UNSUPPORTED = 0x8100,
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PCIBIOS_BADVENDOR = 0x8300,
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PCIBIOS_NODEV = 0x8600,
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PCIBIOS_BADREG = 0x8700
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};
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int int12_handler(struct eregs *regs);
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int int1a_handler(struct eregs *regs);
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int int15_handler(struct eregs *regs);
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int int12_handler(struct eregs *regs)
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{
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regs->eax = 64 * 1024;
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return 0;
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}
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int int1a_handler(struct eregs *regs)
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{
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unsigned short func = (unsigned short)regs->eax;
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int retval = 0;
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unsigned short devid, vendorid, devfn;
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/* Use short to get rid of gabage in upper half of 32-bit register */
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short devindex;
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unsigned char bus;
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struct device *dev;
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switch (func) {
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case PCIBIOS_CHECK:
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regs->edx = 0x20494350; /* ' ICP' */
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regs->edi = 0x00000000; /* protected mode entry */
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retval = 0;
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break;
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case PCIBIOS_FINDDEV:
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devid = regs->ecx;
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vendorid = regs->edx;
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devindex = regs->esi;
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dev = 0;
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#ifdef CONFIG_COREBOOT_V2
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while ((dev = dev_find_device(vendorid, devid, dev))) {
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#else
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while ((dev = dev_find_pci_device(vendorid, devid, dev))) {
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#endif
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if (devindex <= 0)
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break;
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devindex--;
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}
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if (dev) {
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unsigned short busdevfn;
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regs->eax = 0;
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// busnum is an unsigned char;
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// devfn is an int, so we mask it off.
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busdevfn = (dev->bus->secondary << 8)
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| (dev->path.pci.devfn & 0xff);
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printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func, busdevfn);
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regs->ebx = busdevfn;
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retval = 0;
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} else {
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regs->eax = PCIBIOS_NODEV;
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retval = -1;
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}
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break;
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case PCIBIOS_READCONFDWORD:
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case PCIBIOS_READCONFWORD:
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case PCIBIOS_READCONFBYTE:
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case PCIBIOS_WRITECONFDWORD:
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case PCIBIOS_WRITECONFWORD:
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case PCIBIOS_WRITECONFBYTE:
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unsigned long dword;
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unsigned short word;
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unsigned char byte;
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unsigned char reg;
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devfn = regs->ebx & 0xff;
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bus = regs->ebx >> 8;
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reg = regs->edi;
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dev = dev_find_slot(bus, devfn);
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if (!dev) {
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printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn);
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// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
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regs->eax = PCIBIOS_BADREG;
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retval = -1;
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return retval;
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}
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switch (func) {
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case PCIBIOS_READCONFBYTE:
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byte = pci_read_config8(dev, reg);
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regs->ecx = byte;
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break;
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case PCIBIOS_READCONFWORD:
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word = pci_read_config16(dev, reg);
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regs->ecx = word;
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break;
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case PCIBIOS_READCONFDWORD:
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dword = pci_read_config32(dev, reg);
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regs->ecx = dword;
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break;
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case PCIBIOS_WRITECONFBYTE:
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byte = regs->ecx;
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pci_write_config8(dev, reg, byte);
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break;
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case PCIBIOS_WRITECONFWORD:
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word = regs->ecx;
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pci_write_config16(dev, reg, word);
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break;
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case PCIBIOS_WRITECONFDWORD:
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dword = regs->ecx;
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pci_write_config32(dev, reg, dword);
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break;
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}
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printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%x\n",
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func, bus, devfn, reg, regs->ecx);
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regs->eax = 0;
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retval = 0;
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break;
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default:
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printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
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retval = -1;
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break;
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}
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return retval;
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}
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int int15_handler(struct eregs *regs)
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{
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int res = -1;
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/* This int15 handler is VIA Tech. specific. Other chipsets need other
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* handlers. The right way to do this is to move this handler code into
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* the mainboard or northbridge code.
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*/
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switch (regs->eax & 0xffff) {
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case 0x5f19:
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break;
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case 0x5f18:
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regs->eax = 0x5f;
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// MCLK = 133, 32M frame buffer, 256 M main memory
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regs->ebx = 0x545;
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regs->ecx = 0x060;
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res = 0;
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break;
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case 0x5f00:
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regs->eax = 0x8600;
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break;
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case 0x5f01:
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regs->eax = 0x5f;
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regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768
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res = 0;
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break;
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case 0x5f02:
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regs->eax = 0x5f;
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regs->ebx = (regs->ebx & 0xffff0000) | 2;
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regs->ecx = (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only
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regs->edx = (regs->edx & 0xffff0000) | 0; // TV Layout - default
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res = 0;
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break;
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case 0x5f0f:
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regs->eax = 0x860f;
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break;
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/* And now Intel IGD code */
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#define BOOT_DISPLAY_DEFAULT 0
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#define BOOT_DISPLAY_CRT (1 << 0)
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#define BOOT_DISPLAY_TV (1 << 1)
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#define BOOT_DISPLAY_EFP (1 << 2)
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#define BOOT_DISPLAY_LCD (1 << 3)
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#define BOOT_DISPLAY_CRT2 (1 << 4)
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#define BOOT_DISPLAY_TV2 (1 << 5)
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#define BOOT_DISPLAY_EFP2 (1 << 6)
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#define BOOT_DISPLAY_LCD2 (1 << 7)
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case 0x5f35:
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regs->eax = 0x5f;
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regs->ecx = BOOT_DISPLAY_DEFAULT;
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res = 0;
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break;
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case 0x5f40:
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regs->eax = 0x5f;
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regs->ecx = 3; // This is mainboard specific
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printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
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res = 0;
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break;
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default:
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printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
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regs->eax & 0xffff);
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}
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return res;
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}
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