Lee Leahy cff5f09e93 drivers/intel/fsp1_1: Make fsp_run_silicon_init public ... Remove the "static" declaration from fsp_run_silicon_init and declare the routine in ramstage.h. This routine can be called directly when FSP is already in RAM. TEST=Build and run on Galileo Change-Id: Iddb32d00c5d4447eab5c95b0ad5c40309afa293e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13630 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-02-08 18:53:45 +01:00
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acpi	acpi/: add missing license header	2016-01-14 22:52:11 +01:00
arch	xcompile: Add a way to specify -march=i586	2016-02-03 02:58:10 +01:00
commonlib	commonlib: move uefi includes out of commonlib includes	2016-02-02 14:27:03 +01:00
console	console: Simplify bootblock console Kconfig selection logic	2016-01-21 05:37:27 +01:00
cpu	cpu/amd/fam10h-fam15h: Honor CMOS option to disable CPB (core boost)	2016-02-05 22:27:31 +01:00
device	arch/x86: Drop arch/pciconf.h	2016-01-26 20:22:44 +01:00
drivers	drivers/intel/fsp1_1: Make fsp_run_silicon_init public	2016-02-08 18:53:45 +01:00
ec	google/chromeec: implement vboot_(save|retrieve)_hash API	2016-02-04 17:34:58 +01:00
include	include/device: Move inline functions from pci_def.h to pci.h	2016-02-03 03:32:58 +01:00
lib	lib: add bootmode.c to verstage	2016-02-04 17:36:07 +01:00
mainboard	mainboard/intel/galileo: Add board_info.txt	2016-02-05 23:02:57 +01:00
northbridge	nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h	2016-02-05 22:26:54 +01:00
soc	intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown	2016-02-04 17:44:28 +01:00
southbridge	drivers/pc80: Add PS/2 mouse presence detect	2016-02-01 22:10:46 +01:00
superio	drivers/pc80: Add PS/2 mouse presence detect	2016-02-01 22:10:46 +01:00
vendorcode	google/chromeos/vboot2: honor boot region device size	2016-02-04 17:42:54 +01:00
Kconfig	chromeos/vboot: provide support for x86 memory init verification	2016-02-04 17:34:00 +01:00