mirror of
https://github.com/fail0verflow/switch-coreboot.git
synced 2025-05-04 01:39:18 -04:00
ca6312010d
and leaving enough room for a real payload (not /dev/null) This is a wonderful example why "uses" sucks. * add Config-abuild.lb for those boards that dont build with the default settings and a real payload: arima/hdama, amd/quartet, amd/serengeti_cheetah, ibm/e326 * if lzma is installed and a real payload is used, try compressing it. * fix a small bug in "abuild --help" This patch is acked by me because its due to infrastructural changes only. Flames welcome. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
122 lines
2.3 KiB
Text
122 lines
2.3 KiB
Text
##
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## Config file for the Total Impact briQ
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##
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uses TTYS0_DIV
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uses TTYS0_BASE
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uses CONFIG_BRIQ_750FX
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uses CONFIG_BRIQ_7400
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uses ISA_IO_BASE
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uses ISA_MEM_BASE
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uses PCIC0_CFGADDR
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uses PCIC0_CFGDATA
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uses _IO_BASE
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uses CROSS_COMPILE
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uses HAVE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_USE_INIT
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uses NO_POST
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_IDE_STREAM
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uses CONFIG_COMPRESSED_ROM_STREAM_LZMA
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uses IDE_BOOT_DRIVE
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uses IDE_SWAB IDE_OFFSET
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uses ROM_SIZE
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uses _RESET
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uses _EXCEPTION_VECTORS
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uses _ROMBASE
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uses _ROMSTART
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uses _RAMBASE
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uses _RAMSTART
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uses STACK_SIZE
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uses HEAP_SIZE
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uses CONFIG_BRIQ_750FX
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uses CONFIG_BRIQ_7400
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uses CONFIG_SYS_CLK_FREQ
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uses MAINBOARD
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uses MAINBOARD_VENDOR
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uses MAINBOARD_PART_NUMBER
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uses LINUXBIOS_EXTRA_VERSION
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uses CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses OBJCOPY
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##
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## Set memory map
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##
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default ISA_IO_BASE=0x80000000
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default ISA_MEM_BASE=0xc0000000
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default PCIC0_CFGADDR=0xff5f8000
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default PCIC0_CFGDATA=0xff5f8010
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default _IO_BASE=ISA_IO_BASE
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##
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## The briQ uses weird clocking, 4 = 115200
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##
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default TTYS0_DIV=4
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##
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## Set UART base address
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##
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default TTYS0_BASE=0x3f8
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## use a cross compiler
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#default CROSS_COMPILE="powerpc-eabi-"
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#default CROSS_COMPILE="ppc_74xx-"
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## Use stage 1 initialization code
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default CONFIG_USE_INIT=1
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## We don't use compressed image
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default CONFIG_COMPRESS=0
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## Turn off POST codes
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default NO_POST=1
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## Enable serial console
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default DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_CONSOLE_SERIAL8250=1
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## Boot linux from IDE
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default CONFIG_IDE_STREAM=1
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default IDE_BOOT_DRIVE=0
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default IDE_SWAB=1
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default IDE_OFFSET=0
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# ROM is 1Mb
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default ROM_SIZE=1048576
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# Set stack and heap sizes (stage 2)
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default STACK_SIZE=0x10000
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default HEAP_SIZE=0x10000
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##
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## System clock
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##
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default CONFIG_SYS_CLK_FREQ=33
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# Sandpoint Demo Board
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## Base of ROM
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default _ROMBASE=0xfff00000
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## Sandpoint reset vector
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default _RESET=_ROMBASE+0x100
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## Exception vectors (other than reset vector)
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default _EXCEPTION_VECTORS=_RESET+0x100
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## Start of linuxBIOS in the boot rom
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## = _RESET + exeception vector table size
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default _ROMSTART=_RESET+0x3100
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## LinuxBIOS C code runs at this location in RAM
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default _RAMBASE=0x00100000
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default _RAMSTART=0x00100000
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default CONFIG_BRIQ_750FX=1
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#default CONFIG_BRIQ_7400=1
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### End Options.lb
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end
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